From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH 1/3] ARM: dts: at91: add ram bindings
Date: Mon, 23 Aug 2021 13:03:54 +0300 [thread overview]
Message-ID: <20210823100356.22206-2-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210823100356.22206-1-claudiu.beznea@microchip.com>
Add bindings for RAM (controller and PHY). These are necessary
for platform specific power management code.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index cc6be6db7b80..ecabab4343b6 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -515,6 +515,18 @@ spi11: spi@400 {
};
};
+ uddrc: uddrc@e3800000 {
+ compatible = "microchip,sama7g5-uddrc";
+ reg = <0xe3800000 0x4000>;
+ status = "okay";
+ };
+
+ ddr3phy: ddr3phy@e3804000 {
+ compatible = "microchip,sama7g5-ddr3phy";
+ reg = <0xe3804000 0x1000>;
+ status = "okay";
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
--
2.25.1
next prev parent reply other threads:[~2021-08-23 10:04 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 10:03 [PATCH 0/3] ARM: dts: at91: enable ips for sama7g5 Claudiu Beznea
2021-08-23 10:03 ` Claudiu Beznea [this message]
2021-08-23 10:03 ` [PATCH 2/3] ARM: dts: at91: add bindins for securam Claudiu Beznea
2021-08-23 10:03 ` [PATCH 3/3] ARM: dts: at91: add bindings for shdwc Claudiu Beznea
2021-08-23 12:18 ` [PATCH 0/3] ARM: dts: at91: enable ips for sama7g5 Alexandre Belloni
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