From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: will@kernel.org, mathieu.poirier@linaro.org
Cc: catalin.marinas@arm.com, anshuman.khandual@arm.com,
mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v4 08/15] coresight: trbe: Allow driver to choose a different alignment
Date: Tue, 12 Oct 2021 14:17:36 +0100 [thread overview]
Message-ID: <20211012131743.2040596-9-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20211012131743.2040596-1-suzuki.poulose@arm.com>
The TRBE hardware mandates a minimum alignment for the TRBPTR_EL1,
advertised via the TRBIDR_EL1. This is used by the driver to
align the buffer write head. This patch allows the driver to
choose a different alignment from that of the hardware, by
decoupling the alignment tracking. This will be useful for
working around errata.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-trbe.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index 58796ff425a4..f8c04c428780 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -67,8 +67,18 @@ struct trbe_buf {
struct trbe_cpudata *cpudata;
};
+/*
+ * struct trbe_cpudata: TRBE instance specific data
+ * @trbe_flag - TRBE dirty/access flag support
+ * @trbe_hw_align - Actual TRBE alignment required for TRBPTR_EL1.
+ * @trbe_align - Software alignment used for the TRBPTR_EL1,
+ * @cpu - CPU this TRBE belongs to.
+ * @mode - Mode of current operation. (perf/disabled)
+ * @drvdata - TRBE specific drvdata
+ */
struct trbe_cpudata {
bool trbe_flag;
+ u64 trbe_hw_align;
u64 trbe_align;
int cpu;
enum cs_mode mode;
@@ -875,7 +885,7 @@ static ssize_t align_show(struct device *dev, struct device_attribute *attr, cha
{
struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
- return sprintf(buf, "%llx\n", cpudata->trbe_align);
+ return sprintf(buf, "%llx\n", cpudata->trbe_hw_align);
}
static DEVICE_ATTR_RO(align);
@@ -963,11 +973,13 @@ static void arm_trbe_probe_cpu(void *info)
goto cpu_clear;
}
- cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
- if (cpudata->trbe_align > SZ_2K) {
+ cpudata->trbe_hw_align = 1ULL << get_trbe_address_align(trbidr);
+ if (cpudata->trbe_hw_align > SZ_2K) {
pr_err("Unsupported alignment on cpu %d\n", cpu);
goto cpu_clear;
}
+
+ cpudata->trbe_align = cpudata->trbe_hw_align;
cpudata->trbe_flag = get_trbe_flag_update(trbidr);
cpudata->cpu = cpu;
cpudata->drvdata = drvdata;
--
2.25.4
next prev parent reply other threads:[~2021-10-12 13:19 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-12 13:17 [PATCH v4 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-12 15:31 ` Randy Dunlap
2021-10-14 14:17 ` Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose
2021-10-12 15:35 ` Randy Dunlap
2021-10-12 13:17 ` [PATCH v4 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-10-12 13:17 ` Suzuki K Poulose [this message]
2021-10-12 13:17 ` [PATCH v4 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose
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