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From: Samuel Holland <samuel@sholland.org>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	linux-sunxi@lists.linux.dev
Cc: Michael Turquette <mturquette@baylibre.com>,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Stephen Boyd <sboyd@kernel.org>,
	Samuel Holland <samuel@sholland.org>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org
Subject: [PATCH v1 0/6] clk: sunxi-ng: Allwinner D1 clock support
Date: Thu, 18 Nov 2021 22:35:38 -0600	[thread overview]
Message-ID: <20211119043545.4010-1-samuel@sholland.org> (raw)

This series adds support for the D1's CCU and R_CCU.

I attempted to hook up clock parents the "right" way, not using global
names. To accomplish that, I added several new macros. I am open to
comments on this approach. It looks a bit messier, but seems like it
could be less prone to errors.


Samuel Holland (6):
  dt-bindings: clk: Add compatibles for D1 CCUs
  clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw
  clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hw
  clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hw
  clk: sunxi-ng: gate: Add macros for gates with fixed dividers
  clk: sunxi-ng: Add support for the D1 SoC clocks

 .../clock/allwinner,sun4i-a10-ccu.yaml        |    4 +
 drivers/clk/sunxi-ng/Kconfig                  |   10 +
 drivers/clk/sunxi-ng/Makefile                 |    4 +
 drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c        |  140 ++
 drivers/clk/sunxi-ng/ccu-sun20i-d1-r.h        |   17 +
 drivers/clk/sunxi-ng/ccu-sun20i-d1.c          | 1390 +++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun20i-d1.h          |   15 +
 drivers/clk/sunxi-ng/ccu_div.h                |   78 +
 drivers/clk/sunxi-ng/ccu_gate.h               |   32 +-
 drivers/clk/sunxi-ng/ccu_mp.h                 |   49 +
 drivers/clk/sunxi-ng/ccu_mux.h                |   33 +
 include/dt-bindings/clock/sun20i-d1-ccu.h     |  156 ++
 include/dt-bindings/clock/sun20i-d1-r-ccu.h   |   19 +
 include/dt-bindings/reset/sun20i-d1-ccu.h     |   77 +
 include/dt-bindings/reset/sun20i-d1-r-ccu.h   |   16 +
 15 files changed, 2039 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun20i-d1-r.h
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun20i-d1.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun20i-d1.h
 create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h
 create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h
 create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h
 create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h

-- 
2.32.0


             reply	other threads:[~2021-11-19  4:35 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-19  4:35 Samuel Holland [this message]
2021-11-19  4:35 ` [PATCH v1 1/6] dt-bindings: clk: Add compatibles for D1 CCUs Samuel Holland
2021-11-19  4:35 ` [PATCH v1 2/6] clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw Samuel Holland
2021-11-19  4:35 ` [PATCH v1 3/6] clk: sunxi-ng: mp: " Samuel Holland
2021-11-19  4:35 ` [PATCH v1 4/6] clk: sunxi-ng: mux: " Samuel Holland
2021-11-19  4:35 ` [PATCH v1 5/6] clk: sunxi-ng: gate: Add macros for gates with fixed dividers Samuel Holland
2021-11-19  4:35 ` [PATCH v1 6/6] clk: sunxi-ng: Add support for the D1 SoC clocks Samuel Holland
2021-11-22  9:06 ` [PATCH v1 0/6] clk: sunxi-ng: Allwinner D1 clock support Maxime Ripard

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