From: Samuel Holland <samuel@sholland.org>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
linux-sunxi@lists.linux.dev
Cc: Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Stephen Boyd <sboyd@kernel.org>,
Samuel Holland <samuel@sholland.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v1 4/6] clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hw
Date: Thu, 18 Nov 2021 22:35:42 -0600 [thread overview]
Message-ID: <20211119043545.4010-5-samuel@sholland.org> (raw)
In-Reply-To: <20211119043545.4010-1-samuel@sholland.org>
Referencing parents with clk_hw pointers is more efficient and removes
the dependency on global clock names. clk_parent_data is needed when
some parent clocks are provided from another driver. Add macros for
declaring muxes that take advantage of these.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi-ng/ccu_mux.h | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index e31efc509b3d..2c1811a445b0 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -72,6 +72,39 @@ struct ccu_mux {
SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
_reg, _shift, _width, 0, _flags)
+#define SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \
+ _shift, _width, _gate, _flags) \
+ struct ccu_mux _struct = { \
+ .enable = _gate, \
+ .mux = _SUNXI_CCU_MUX(_shift, _width), \
+ .common = { \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
+ _parents, \
+ &ccu_mux_ops, \
+ _flags), \
+ } \
+ }
+
+#define SUNXI_CCU_MUX_DATA(_struct, _name, _parents, _reg, \
+ _shift, _width, _flags) \
+ SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \
+ _shift, _width, 0, _flags)
+
+#define SUNXI_CCU_MUX_HW_WITH_GATE(_struct, _name, _parents, _reg, \
+ _shift, _width, _gate, _flags) \
+ struct ccu_mux _struct = { \
+ .enable = _gate, \
+ .mux = _SUNXI_CCU_MUX(_shift, _width), \
+ .common = { \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
+ _parents, \
+ &ccu_mux_ops, \
+ _flags), \
+ } \
+ }
+
static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);
--
2.32.0
next prev parent reply other threads:[~2021-11-19 4:36 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-19 4:35 [PATCH v1 0/6] clk: sunxi-ng: Allwinner D1 clock support Samuel Holland
2021-11-19 4:35 ` [PATCH v1 1/6] dt-bindings: clk: Add compatibles for D1 CCUs Samuel Holland
2021-11-19 4:35 ` [PATCH v1 2/6] clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw Samuel Holland
2021-11-19 4:35 ` [PATCH v1 3/6] clk: sunxi-ng: mp: " Samuel Holland
2021-11-19 4:35 ` Samuel Holland [this message]
2021-11-19 4:35 ` [PATCH v1 5/6] clk: sunxi-ng: gate: Add macros for gates with fixed dividers Samuel Holland
2021-11-19 4:35 ` [PATCH v1 6/6] clk: sunxi-ng: Add support for the D1 SoC clocks Samuel Holland
2021-11-22 9:06 ` [PATCH v1 0/6] clk: sunxi-ng: Allwinner D1 clock support Maxime Ripard
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