* [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI nodes
@ 2021-12-09 12:36 Tudor Ambarus
2021-12-09 12:36 ` [PATCH 2/2] ARM: dts: at91: sama7g5ek: Add QSPI0 node Tudor Ambarus
2021-12-13 13:59 ` [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI nodes Nicolas Ferre
0 siblings, 2 replies; 3+ messages in thread
From: Tudor Ambarus @ 2021-12-09 12:36 UTC (permalink / raw)
To: robh+dt, nicolas.ferre
Cc: alexandre.belloni, ludovic.desroches, devicetree,
linux-arm-kernel, linux-kernel, Tudor Ambarus
sama7g5 embedds 2 instances of QSPI controller:
1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
and OctaFlash Protocols Supported.
2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
arch/arm/boot/dts/sama7g5.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 7039311bf678..eddcfbf4d223 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -181,6 +181,36 @@ tcb1: timer@e0800000 {
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
+ qspi0: spi@e080c000 {
+ compatible = "microchip,sama7g5-ospi";
+ reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>,
+ <&dma0 AT91_XDMAC_DT_PERID(40)>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
+ clock-names = "pclk", "gclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi1: spi@e0810000 {
+ compatible = "microchip,sama7g5-qspi";
+ reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>,
+ <&dma0 AT91_XDMAC_DT_PERID(42)>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
+ clock-names = "pclk", "gclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
adc: adc@e1000000 {
compatible = "microchip,sama7g5-adc";
reg = <0xe1000000 0x200>;
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH 2/2] ARM: dts: at91: sama7g5ek: Add QSPI0 node
2021-12-09 12:36 [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI nodes Tudor Ambarus
@ 2021-12-09 12:36 ` Tudor Ambarus
2021-12-13 13:59 ` [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI nodes Nicolas Ferre
1 sibling, 0 replies; 3+ messages in thread
From: Tudor Ambarus @ 2021-12-09 12:36 UTC (permalink / raw)
To: robh+dt, nicolas.ferre
Cc: alexandre.belloni, ludovic.desroches, devicetree,
linux-arm-kernel, linux-kernel, Tudor Ambarus
QSPI0 comunicates with a MX66LM1G45G SPI NOR flash.
Enable the controller and describe the flash.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
arch/arm/boot/dts/at91-sama7g5ek.dts | 73 ++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index 0e1975c6812e..ccf9e224da78 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
@@ -13,6 +13,7 @@
#include "sama7g5.dtsi"
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/at91.h>
/ {
model = "Microchip SAMA7G5-EK";
@@ -134,6 +135,59 @@ &cpu0 {
cpu-supply = <&vddcpu>;
};
+&qspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <133000000>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ m25p,fast-read;
+
+ at91bootstrap@0 {
+ label = "ospi: at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "ospi: bootloader";
+ reg = <0x40000 0xc0000>;
+ };
+
+ bootloaderenvred@100000 {
+ label = "ospi: bootloader env redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ bootloaderenv@140000 {
+ label = "ospi: bootloader env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "ospi: device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "ospi: kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "ospi: rootfs";
+ reg = <0x800000 0x7800000>;
+ };
+
+ };
+};
+
&dma0 {
status = "okay";
};
@@ -555,6 +609,25 @@ pinctrl_mikrobus1_spi: mikrobus1_spi {
bias-disable;
};
+ pinctrl_qspi: qspi {
+ pinmux = <PIN_PB12__QSPI0_IO0>,
+ <PIN_PB11__QSPI0_IO1>,
+ <PIN_PB10__QSPI0_IO2>,
+ <PIN_PB9__QSPI0_IO3>,
+ <PIN_PB16__QSPI0_IO4>,
+ <PIN_PB17__QSPI0_IO5>,
+ <PIN_PB18__QSPI0_IO6>,
+ <PIN_PB19__QSPI0_IO7>,
+ <PIN_PB13__QSPI0_CS>,
+ <PIN_PB14__QSPI0_SCK>,
+ <PIN_PB15__QSPI0_SCKN>,
+ <PIN_PB20__QSPI0_DQS>,
+ <PIN_PB21__QSPI0_INT>;
+ bias-disable;
+ slew-rate = <0>;
+ atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;
+ };
+
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_data {
pinmux = <PIN_PA1__SDMMC0_CMD>,
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI nodes
2021-12-09 12:36 [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI nodes Tudor Ambarus
2021-12-09 12:36 ` [PATCH 2/2] ARM: dts: at91: sama7g5ek: Add QSPI0 node Tudor Ambarus
@ 2021-12-13 13:59 ` Nicolas Ferre
1 sibling, 0 replies; 3+ messages in thread
From: Nicolas Ferre @ 2021-12-13 13:59 UTC (permalink / raw)
To: Tudor Ambarus, robh+dt
Cc: alexandre.belloni, ludovic.desroches, devicetree,
linux-arm-kernel, linux-kernel
On 09/12/2021 at 13:36, Tudor Ambarus wrote:
> sama7g5 embedds 2 instances of QSPI controller:
> 1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
> and OctaFlash Protocols Supported.
> 2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Looks good to me: integrated in at91-dt for 5.17.
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Best regards,
Nicolas
> ---
> arch/arm/boot/dts/sama7g5.dtsi | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
> index 7039311bf678..eddcfbf4d223 100644
> --- a/arch/arm/boot/dts/sama7g5.dtsi
> +++ b/arch/arm/boot/dts/sama7g5.dtsi
> @@ -181,6 +181,36 @@ tcb1: timer@e0800000 {
> clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
> };
>
> + qspi0: spi@e080c000 {
> + compatible = "microchip,sama7g5-ospi";
> + reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
> + reg-names = "qspi_base", "qspi_mmap";
> + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>,
> + <&dma0 AT91_XDMAC_DT_PERID(40)>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
> + clock-names = "pclk", "gclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + qspi1: spi@e0810000 {
> + compatible = "microchip,sama7g5-qspi";
> + reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
> + reg-names = "qspi_base", "qspi_mmap";
> + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>,
> + <&dma0 AT91_XDMAC_DT_PERID(42)>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
> + clock-names = "pclk", "gclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> adc: adc@e1000000 {
> compatible = "microchip,sama7g5-adc";
> reg = <0xe1000000 0x200>;
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-12-13 13:59 UTC | newest]
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2021-12-09 12:36 [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI nodes Tudor Ambarus
2021-12-09 12:36 ` [PATCH 2/2] ARM: dts: at91: sama7g5ek: Add QSPI0 node Tudor Ambarus
2021-12-13 13:59 ` [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI nodes Nicolas Ferre
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