* [PATCH] RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode
@ 2022-01-31 11:03 Mayuresh Chitale
2022-02-02 11:14 ` Anup Patel
0 siblings, 1 reply; 4+ messages in thread
From: Mayuresh Chitale @ 2022-01-31 11:03 UTC (permalink / raw)
To: anup
Cc: atishp, palmer, kvm-riscv, linux-riscv, linux-kernel, Mayuresh Chitale
Those applications that run in VU mode and access the time CSR cause
a virtual instruction trap as Guest kernel currently does not
initialize the scounteren CSR.
To fix this, we should make CY, TM, and IR counters accessibile
by default in VU mode (similar to OpenSBI).
Fixes: a33c72faf2d73 ("RISC-V: KVM: Implement VCPU create, init and
destroy functions")
Cc:stable@vger.kernel.org
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
arch/riscv/kvm/vcpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 0c5239e05721..caaf824347b9 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -90,6 +90,7 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
{
struct kvm_cpu_context *cntx;
+ struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
/* Mark this VCPU never ran */
vcpu->arch.ran_atleast_once = false;
@@ -106,6 +107,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
cntx->hstatus |= HSTATUS_SPVP;
cntx->hstatus |= HSTATUS_SPV;
+ /* By default, make CY, TM, and IR counters accessible in VU mode */
+ reset_csr->scounteren=0x7;
+
/* Setup VCPU timer */
kvm_riscv_vcpu_timer_init(vcpu);
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode
2022-01-31 11:03 [PATCH] RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode Mayuresh Chitale
@ 2022-02-02 11:14 ` Anup Patel
2022-02-02 13:19 ` Jessica Clarke
0 siblings, 1 reply; 4+ messages in thread
From: Anup Patel @ 2022-02-02 11:14 UTC (permalink / raw)
To: Mayuresh Chitale
Cc: Atish Patra, Palmer Dabbelt, kvm-riscv, linux-riscv,
linux-kernel@vger.kernel.org List
On Mon, Jan 31, 2022 at 4:33 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> Those applications that run in VU mode and access the time CSR cause
> a virtual instruction trap as Guest kernel currently does not
> initialize the scounteren CSR.
>
> To fix this, we should make CY, TM, and IR counters accessibile
> by default in VU mode (similar to OpenSBI).
>
> Fixes: a33c72faf2d73 ("RISC-V: KVM: Implement VCPU create, init and
> destroy functions")
> Cc:stable@vger.kernel.org
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Thanks, I have queued this for fixes.
Regards,
Anup
> ---
> arch/riscv/kvm/vcpu.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 0c5239e05721..caaf824347b9 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -90,6 +90,7 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
> int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
> {
> struct kvm_cpu_context *cntx;
> + struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
>
> /* Mark this VCPU never ran */
> vcpu->arch.ran_atleast_once = false;
> @@ -106,6 +107,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
> cntx->hstatus |= HSTATUS_SPVP;
> cntx->hstatus |= HSTATUS_SPV;
>
> + /* By default, make CY, TM, and IR counters accessible in VU mode */
> + reset_csr->scounteren=0x7;
> +
> /* Setup VCPU timer */
> kvm_riscv_vcpu_timer_init(vcpu);
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode
2022-02-02 11:14 ` Anup Patel
@ 2022-02-02 13:19 ` Jessica Clarke
2022-02-02 13:29 ` Anup Patel
0 siblings, 1 reply; 4+ messages in thread
From: Jessica Clarke @ 2022-02-02 13:19 UTC (permalink / raw)
To: Anup Patel
Cc: Mayuresh Chitale, Atish Patra, Palmer Dabbelt, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List
On 2 Feb 2022, at 11:14, Anup Patel <anup@brainfault.org> wrote:
>
> On Mon, Jan 31, 2022 at 4:33 PM Mayuresh Chitale
> <mchitale@ventanamicro.com> wrote:
>>
>> Those applications that run in VU mode and access the time CSR cause
>> a virtual instruction trap as Guest kernel currently does not
>> initialize the scounteren CSR.
>>
>> To fix this, we should make CY, TM, and IR counters accessibile
>> by default in VU mode (similar to OpenSBI).
>>
>> Fixes: a33c72faf2d73 ("RISC-V: KVM: Implement VCPU create, init and
>> destroy functions")
>> Cc:stable@vger.kernel.org
>> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
>
> Thanks, I have queued this for fixes.
The formatting is clearly wrong...
> Regards,
> Anup
>
>> ---
>> arch/riscv/kvm/vcpu.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
>> index 0c5239e05721..caaf824347b9 100644
>> --- a/arch/riscv/kvm/vcpu.c
>> +++ b/arch/riscv/kvm/vcpu.c
>> @@ -90,6 +90,7 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
>> int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
>> {
>> struct kvm_cpu_context *cntx;
>> + struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
>>
>> /* Mark this VCPU never ran */
>> vcpu->arch.ran_atleast_once = false;
>> @@ -106,6 +107,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
>> cntx->hstatus |= HSTATUS_SPVP;
>> cntx->hstatus |= HSTATUS_SPV;
>>
>> + /* By default, make CY, TM, and IR counters accessible in VU mode */
>> + reset_csr->scounteren=0x7;
... here
Jess
>> +
>> /* Setup VCPU timer */
>> kvm_riscv_vcpu_timer_init(vcpu);
>>
>> --
>> 2.25.1
>>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode
2022-02-02 13:19 ` Jessica Clarke
@ 2022-02-02 13:29 ` Anup Patel
0 siblings, 0 replies; 4+ messages in thread
From: Anup Patel @ 2022-02-02 13:29 UTC (permalink / raw)
To: Jessica Clarke
Cc: Anup Patel, Mayuresh Chitale, Atish Patra, Palmer Dabbelt,
kvm-riscv, linux-riscv, linux-kernel@vger.kernel.org List
On Wed, Feb 2, 2022 at 6:49 PM Jessica Clarke <jrtc27@jrtc27.com> wrote:
>
> On 2 Feb 2022, at 11:14, Anup Patel <anup@brainfault.org> wrote:
> >
> > On Mon, Jan 31, 2022 at 4:33 PM Mayuresh Chitale
> > <mchitale@ventanamicro.com> wrote:
> >>
> >> Those applications that run in VU mode and access the time CSR cause
> >> a virtual instruction trap as Guest kernel currently does not
> >> initialize the scounteren CSR.
> >>
> >> To fix this, we should make CY, TM, and IR counters accessibile
> >> by default in VU mode (similar to OpenSBI).
> >>
> >> Fixes: a33c72faf2d73 ("RISC-V: KVM: Implement VCPU create, init and
> >> destroy functions")
> >> Cc:stable@vger.kernel.org
> >> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> >
> > Thanks, I have queued this for fixes.
>
> The formatting is clearly wrong...
I have updated this in my fixes queue.
>
> > Regards,
> > Anup
> >
> >> ---
> >> arch/riscv/kvm/vcpu.c | 4 ++++
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> >> index 0c5239e05721..caaf824347b9 100644
> >> --- a/arch/riscv/kvm/vcpu.c
> >> +++ b/arch/riscv/kvm/vcpu.c
> >> @@ -90,6 +90,7 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
> >> int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
> >> {
> >> struct kvm_cpu_context *cntx;
> >> + struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
> >>
> >> /* Mark this VCPU never ran */
> >> vcpu->arch.ran_atleast_once = false;
> >> @@ -106,6 +107,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
> >> cntx->hstatus |= HSTATUS_SPVP;
> >> cntx->hstatus |= HSTATUS_SPV;
> >>
> >> + /* By default, make CY, TM, and IR counters accessible in VU mode */
> >> + reset_csr->scounteren=0x7;
>
> ... here
Same as above, I have updated this my queue as well.
Thanks,
Anup
>
> Jess
>
> >> +
> >> /* Setup VCPU timer */
> >> kvm_riscv_vcpu_timer_init(vcpu);
> >>
> >> --
> >> 2.25.1
> >>
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-01-31 11:03 [PATCH] RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode Mayuresh Chitale
2022-02-02 11:14 ` Anup Patel
2022-02-02 13:19 ` Jessica Clarke
2022-02-02 13:29 ` Anup Patel
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