From: James Clark <james.clark@arm.com>
To: suzuki.poulose@arm.com, mathieu.poirier@linaro.org,
coresight@lists.linaro.org
Cc: leo.yan@linaro.com, mike.leach@linaro.org,
James Clark <james.clark@arm.com>, Leo Yan <leo.yan@linaro.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 12/15] coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn register accesses consistent with sysreg.h
Date: Thu, 3 Feb 2022 12:06:00 +0000 [thread overview]
Message-ID: <20220203120604.128396-13-james.clark@arm.com> (raw)
In-Reply-To: <20220203120604.128396-1-james.clark@arm.com>
This is a no-op change for style and consistency and has no effect on the
binary produced by gcc-11.
Signed-off-by: James Clark <james.clark@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 +++---
drivers/hwtracing/coresight/coresight-etm4x.h | 5 +++++
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 2f7ea60fd003..e134bdabebcf 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -443,7 +443,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
for (i = 0; i < drvdata->nr_ss_cmp; i++) {
/* always clear status bit on restart if using single-shot */
if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
- config->ss_status[i] &= ~BIT(31);
+ config->ss_status[i] &= ~TRCSSCSRn_STATUS;
etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
if (etm4x_sspcicrn_present(drvdata, i))
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 51f6e13e3b29..7d9372ba1168 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1793,9 +1793,9 @@ static ssize_t sshot_ctrl_store(struct device *dev,
spin_lock(&drvdata->spinlock);
idx = config->ss_idx;
- config->ss_ctrl[idx] = val & GENMASK(24, 0);
+ config->ss_ctrl[idx] = val & (TRCSSCCRn_SAC_ARC_RST_MASK << TRCSSCCRn_SAC_ARC_RST_SHIFT);
/* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~BIT(31);
+ config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
spin_unlock(&drvdata->spinlock);
return size;
}
@@ -1845,7 +1845,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
idx = config->ss_idx;
config->ss_pe_cmp[idx] = val & GENMASK(7, 0);
/* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~BIT(31);
+ config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
spin_unlock(&drvdata->spinlock);
return size;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 5701d970d81a..9c22a5b0777f 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -246,6 +246,11 @@
#define TRCACATRn_CONTEXT_MASK GENMASK(2, 0)
#define TRCACATRn_EXLEVEL_SHIFT 8
#define TRCACATRn_EXLEVEL_MASK GENMASK(6, 0)
+
+#define TRCSSCSRn_STATUS BIT(31)
+#define TRCSSCCRn_SAC_ARC_RST_SHIFT 0
+#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
+
/*
* System instructions to access ETM registers.
* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
--
2.28.0
next prev parent reply other threads:[~2022-02-03 12:06 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-03 12:05 [PATCH v2 00/15] Make ETM " James Clark
2022-02-03 12:05 ` [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 " James Clark
2022-02-07 5:44 ` Anshuman Khandual
2022-02-07 19:02 ` Mathieu Poirier
2022-02-08 15:04 ` Suzuki K Poulose
2022-02-09 9:32 ` Mike Leach
2022-02-25 16:28 ` James Clark
2022-02-08 11:36 ` Mike Leach
2022-02-03 12:05 ` [PATCH v2 02/15] coresight: Make ETM4x TRCIDR2 " James Clark
2022-02-03 12:05 ` [PATCH v2 03/15] coresight: Make ETM4x TRCIDR3 " James Clark
2022-02-03 12:05 ` [PATCH v2 04/15] coresight: Make ETM4x TRCIDR4 " James Clark
2022-02-03 12:05 ` [PATCH v2 05/15] coresight: Make ETM4x TRCIDR5 " James Clark
2022-02-03 12:05 ` [PATCH v2 06/15] coresight: Make ETM4x TRCCONFIGR " James Clark
2022-02-03 12:05 ` [PATCH v2 07/15] coresight: Make ETM4x TRCEVENTCTL1R " James Clark
2022-02-07 19:03 ` Mathieu Poirier
2022-02-03 12:05 ` [PATCH v2 08/15] coresight: Make ETM4x TRCSTALLCTLR " James Clark
2022-02-03 12:05 ` [PATCH v2 09/15] coresight: Make ETM4x TRCVICTLR " James Clark
2022-02-03 12:05 ` [PATCH v2 10/15] coresight: Make ETM3x ETMTECR1 " James Clark
2022-02-03 12:05 ` [PATCH v2 11/15] coresight: Make ETM4x TRCACATRn " James Clark
2022-02-03 12:06 ` James Clark [this message]
2022-02-03 12:06 ` [PATCH v2 13/15] coresight: Make ETM4x TRCSSPCICRn " James Clark
2022-02-03 12:06 ` [PATCH v2 14/15] coresight: Make ETM4x TRCBBCTLR " James Clark
2022-02-03 12:06 ` [PATCH v2 15/15] coresight: Make ETM4x TRCRSCTLRn " James Clark
2022-02-08 18:58 ` Mathieu Poirier
2022-02-07 5:51 ` [PATCH v2 00/15] Make ETM " Anshuman Khandual
2022-02-07 10:03 ` James Clark
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