From: James Clark <james.clark@arm.com>
To: suzuki.poulose@arm.com, mathieu.poirier@linaro.org,
coresight@lists.linaro.org
Cc: leo.yan@linaro.com, mike.leach@linaro.org,
James Clark <james.clark@arm.com>, Leo Yan <leo.yan@linaro.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 06/15] coresight: Make ETM4x TRCCONFIGR register accesses consistent with sysreg.h
Date: Thu, 3 Feb 2022 12:05:54 +0000 [thread overview]
Message-ID: <20220203120604.128396-7-james.clark@arm.com> (raw)
In-Reply-To: <20220203120604.128396-1-james.clark@arm.com>
This is a no-op change for style and consistency and has no effect on the
binary produced by gcc-11.
Signed-off-by: James Clark <james.clark@arm.com>
---
.../coresight/coresight-etm4x-core.c | 10 ++--
.../coresight/coresight-etm4x-sysfs.c | 46 +++++++++----------
drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++
3 files changed, 45 insertions(+), 28 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 0f0628968bfd..dc936fb1cc74 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -633,7 +633,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
/* Go from generic option to ETMv4 specifics */
if (attr->config & BIT(ETM_OPT_CYCACC)) {
- config->cfg |= BIT(4);
+ config->cfg |= TRCCONFIGR_CCI;
/* TRM: Must program this for cycacc to work */
config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
}
@@ -653,12 +653,12 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
goto out;
/* bit[11], Global timestamp tracing bit */
- config->cfg |= BIT(11);
+ config->cfg |= TRCCONFIGR_TS;
}
if (attr->config & BIT(ETM_OPT_CTXTID))
/* bit[6], Context ID tracing bit */
- config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
+ config->cfg |= TRCCONFIGR_CID;
/*
* If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
@@ -670,13 +670,13 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
ret = -EINVAL;
goto out;
}
- config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT);
+ config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
}
/* return stack - enable if selected and supported */
if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
/* bit[12], Return stack enable bit */
- config->cfg |= BIT(12);
+ config->cfg |= TRCCONFIGR_RS;
/*
* Set any selected configuration and preset.
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 57e94424a8d6..4c29ab4464a0 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -180,12 +180,12 @@ static ssize_t reset_store(struct device *dev,
/* Disable data tracing: do not trace load and store data transfers */
config->mode &= ~(ETM_MODE_LOAD | ETM_MODE_STORE);
- config->cfg &= ~(BIT(1) | BIT(2));
+ config->cfg &= ~(TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE);
/* Disable data value and data address tracing */
config->mode &= ~(ETM_MODE_DATA_TRACE_ADDR |
ETM_MODE_DATA_TRACE_VAL);
- config->cfg &= ~(BIT(16) | BIT(17));
+ config->cfg &= ~(TRCCONFIGR_DA | TRCCONFIGR_DV);
/* Disable all events tracing */
config->eventctrl0 = 0x0;
@@ -304,82 +304,82 @@ static ssize_t mode_store(struct device *dev,
if (drvdata->instrp0 == true) {
/* start by clearing instruction P0 field */
- config->cfg &= ~(BIT(1) | BIT(2));
+ config->cfg &= ~TRCCONFIGR_INSTP0_LOAD_STORE;
if (config->mode & ETM_MODE_LOAD)
/* 0b01 Trace load instructions as P0 instructions */
- config->cfg |= BIT(1);
+ config->cfg |= TRCCONFIGR_INSTP0_LOAD;
if (config->mode & ETM_MODE_STORE)
/* 0b10 Trace store instructions as P0 instructions */
- config->cfg |= BIT(2);
+ config->cfg |= TRCCONFIGR_INSTP0_STORE;
if (config->mode & ETM_MODE_LOAD_STORE)
/*
* 0b11 Trace load and store instructions
* as P0 instructions
*/
- config->cfg |= BIT(1) | BIT(2);
+ config->cfg |= TRCCONFIGR_INSTP0_LOAD_STORE;
}
/* bit[3], Branch broadcast mode */
if ((config->mode & ETM_MODE_BB) && (drvdata->trcbb == true))
- config->cfg |= BIT(3);
+ config->cfg |= TRCCONFIGR_BB;
else
- config->cfg &= ~BIT(3);
+ config->cfg &= ~TRCCONFIGR_BB;
/* bit[4], Cycle counting instruction trace bit */
if ((config->mode & ETMv4_MODE_CYCACC) &&
(drvdata->trccci == true))
- config->cfg |= BIT(4);
+ config->cfg |= TRCCONFIGR_CCI;
else
- config->cfg &= ~BIT(4);
+ config->cfg &= ~TRCCONFIGR_CCI;
/* bit[6], Context ID tracing bit */
if ((config->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size))
- config->cfg |= BIT(6);
+ config->cfg |= TRCCONFIGR_CID;
else
- config->cfg &= ~BIT(6);
+ config->cfg &= ~TRCCONFIGR_CID;
if ((config->mode & ETM_MODE_VMID) && (drvdata->vmid_size))
- config->cfg |= BIT(7);
+ config->cfg |= TRCCONFIGR_VMID;
else
- config->cfg &= ~BIT(7);
+ config->cfg &= ~TRCCONFIGR_VMID;
/* bits[10:8], Conditional instruction tracing bit */
mode = ETM_MODE_COND(config->mode);
if (drvdata->trccond == true) {
- config->cfg &= ~(BIT(8) | BIT(9) | BIT(10));
- config->cfg |= mode << 8;
+ config->cfg &= ~(TRCCONFIGR_COND_MASK << TRCCONFIGR_COND_SHIFT);
+ config->cfg |= mode << TRCCONFIGR_COND_SHIFT;
}
/* bit[11], Global timestamp tracing bit */
if ((config->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size))
- config->cfg |= BIT(11);
+ config->cfg |= TRCCONFIGR_TS;
else
- config->cfg &= ~BIT(11);
+ config->cfg &= ~TRCCONFIGR_TS;
/* bit[12], Return stack enable bit */
if ((config->mode & ETM_MODE_RETURNSTACK) &&
(drvdata->retstack == true))
- config->cfg |= BIT(12);
+ config->cfg |= TRCCONFIGR_RS;
else
- config->cfg &= ~BIT(12);
+ config->cfg &= ~TRCCONFIGR_RS;
/* bits[14:13], Q element enable field */
mode = ETM_MODE_QELEM(config->mode);
/* start by clearing QE bits */
- config->cfg &= ~(BIT(13) | BIT(14));
+ config->cfg &= ~(TRCCONFIGR_QE_W_COUNTS | TRCCONFIGR_QE_WO_COUNTS);
/*
* if supported, Q elements with instruction counts are enabled.
* Always set the low bit for any requested mode. Valid combos are
* 0b00, 0b01 and 0b11.
*/
if (mode && drvdata->q_support)
- config->cfg |= BIT(13);
+ config->cfg |= TRCCONFIGR_QE_W_COUNTS;
/*
* if supported, Q elements with and without instruction
* counts are enabled
*/
if ((mode & BIT(1)) && (drvdata->q_support & BIT(1)))
- config->cfg |= BIT(14);
+ config->cfg |= TRCCONFIGR_QE_WO_COUNTS;
/* bit[11], AMBA Trace Bus (ATB) trigger enable bit */
if ((config->mode & ETM_MODE_ATB_TRIGGER) &&
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index ca6ed39ceaf7..55e756020a94 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -194,6 +194,23 @@
#define TRCIDR5_NUMCNTR_SHIFT 28
#define TRCIDR5_NUMCNTR_MASK GENMASK(2, 0)
+#define TRCCONFIGR_INSTP0_LOAD BIT(1)
+#define TRCCONFIGR_INSTP0_STORE BIT(2)
+#define TRCCONFIGR_INSTP0_LOAD_STORE (TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE)
+#define TRCCONFIGR_BB BIT(3)
+#define TRCCONFIGR_CCI BIT(4)
+#define TRCCONFIGR_CID BIT(6)
+#define TRCCONFIGR_VMID BIT(7)
+#define TRCCONFIGR_COND_SHIFT 8
+#define TRCCONFIGR_COND_MASK GENMASK(2, 0)
+#define TRCCONFIGR_TS BIT(11)
+#define TRCCONFIGR_RS BIT(12)
+#define TRCCONFIGR_QE_W_COUNTS BIT(13)
+#define TRCCONFIGR_QE_WO_COUNTS BIT(14)
+#define TRCCONFIGR_VMIDOPT BIT(15)
+#define TRCCONFIGR_DA BIT(16)
+#define TRCCONFIGR_DV BIT(17)
+
/*
* System instructions to access ETM registers.
* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
--
2.28.0
next prev parent reply other threads:[~2022-02-03 12:06 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-03 12:05 [PATCH v2 00/15] Make ETM " James Clark
2022-02-03 12:05 ` [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 " James Clark
2022-02-07 5:44 ` Anshuman Khandual
2022-02-07 19:02 ` Mathieu Poirier
2022-02-08 15:04 ` Suzuki K Poulose
2022-02-09 9:32 ` Mike Leach
2022-02-25 16:28 ` James Clark
2022-02-08 11:36 ` Mike Leach
2022-02-03 12:05 ` [PATCH v2 02/15] coresight: Make ETM4x TRCIDR2 " James Clark
2022-02-03 12:05 ` [PATCH v2 03/15] coresight: Make ETM4x TRCIDR3 " James Clark
2022-02-03 12:05 ` [PATCH v2 04/15] coresight: Make ETM4x TRCIDR4 " James Clark
2022-02-03 12:05 ` [PATCH v2 05/15] coresight: Make ETM4x TRCIDR5 " James Clark
2022-02-03 12:05 ` James Clark [this message]
2022-02-03 12:05 ` [PATCH v2 07/15] coresight: Make ETM4x TRCEVENTCTL1R " James Clark
2022-02-07 19:03 ` Mathieu Poirier
2022-02-03 12:05 ` [PATCH v2 08/15] coresight: Make ETM4x TRCSTALLCTLR " James Clark
2022-02-03 12:05 ` [PATCH v2 09/15] coresight: Make ETM4x TRCVICTLR " James Clark
2022-02-03 12:05 ` [PATCH v2 10/15] coresight: Make ETM3x ETMTECR1 " James Clark
2022-02-03 12:05 ` [PATCH v2 11/15] coresight: Make ETM4x TRCACATRn " James Clark
2022-02-03 12:06 ` [PATCH v2 12/15] coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn " James Clark
2022-02-03 12:06 ` [PATCH v2 13/15] coresight: Make ETM4x TRCSSPCICRn " James Clark
2022-02-03 12:06 ` [PATCH v2 14/15] coresight: Make ETM4x TRCBBCTLR " James Clark
2022-02-03 12:06 ` [PATCH v2 15/15] coresight: Make ETM4x TRCRSCTLRn " James Clark
2022-02-08 18:58 ` Mathieu Poirier
2022-02-07 5:51 ` [PATCH v2 00/15] Make ETM " Anshuman Khandual
2022-02-07 10:03 ` James Clark
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