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From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<michals@xilinx.com>,
	Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Subject: [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port
Date: Tue, 15 Feb 2022 18:16:04 +0530	[thread overview]
Message-ID: <20220215124606.28627-1-bharat.kumar.gogada@xilinx.com> (raw)

Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
  to enable and handle legacy interrupts.

Changes in v2:
- changed commit message.

Bharat Kumar Gogada (2):
  dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

 .../bindings/pci/xilinx-versal-cpm.yaml       | 47 ++++++++++++++++---
 drivers/pci/controller/pcie-xilinx-cpm.c      | 33 ++++++++++++-
 2 files changed, 72 insertions(+), 8 deletions(-)

-- 
2.17.1


             reply	other threads:[~2022-02-15 12:46 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-15 12:46 Bharat Kumar Gogada [this message]
2022-02-15 12:46 ` [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada
2022-03-02 15:37   ` Lorenzo Pieralisi
2022-03-03  4:36     ` Bharat Kumar Gogada
2022-02-15 12:46 ` [PATCH v2 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
2022-03-02 15:33   ` Lorenzo Pieralisi
2022-03-03  9:25     ` Bharat Kumar Gogada
2022-03-02  9:37 ` [PATCH v2 0/2] Add support for Xilinx " Bharat Kumar Gogada

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