From: Hari Prasath <Hari.PrasathGE@microchip.com>
To: <nicolas.ferre@microchip.com>, <claudiu.beznea@microchip.com>,
<davem@davemloft.net>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux@armlinux.org.uk>
Cc: <Hari.PrasathGE@microchip.com>
Subject: [PATCH] 2/3] ARM: dts: at91: sama7g5: Add can controllers of sama7g5
Date: Tue, 22 Feb 2022 17:09:23 +0530 [thread overview]
Message-ID: <20220222113924.25799-2-Hari.PrasathGE@microchip.com> (raw)
In-Reply-To: <20220222113924.25799-1-Hari.PrasathGE@microchip.com>
Add support for all the six CAN controllers of sama7g5.The internal SRAM of 128KB
is split among the CAN controllers for the message RAM elements leaving a small
portion reserved for power management. The SRAM split up is as below.
Lower 64K:
PM 13K
can-0 17K
can-1 17K
can-2 17K
Higher 64K:
can-3 17K
can-4 17K
can-5 17K
Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
---
arch/arm/boot/dts/sama7g5.dtsi | 96 ++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 6c7012f74b10..d4d87db8e212 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -211,6 +211,102 @@
status = "disabled";
};
+ can0: can@e0828000 {
+ compatible = "bosch,m_can";
+ reg = <0xe0828000 0x100>, <0x100000 0x7800>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
+ status = "disabled";
+ };
+
+ can1: can@e082c000 {
+ compatible = "bosch,m_can";
+ reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
+ status = "disabled";
+ };
+
+ can2: can@e0830000 {
+ compatible = "bosch,m_can";
+ reg = <0xe0830000 0x100>, <0x100000 0x10000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
+ status = "disabled";
+ };
+
+ can3: can@e0834000 {
+ compatible = "bosch,m_can";
+ reg = <0xe0834000 0x100>, <0x110000 0x4400>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
+ status = "disabled";
+ };
+
+ can4: can@e0838000 {
+ compatible = "bosch,m_can";
+ reg = <0xe0838000 0x100>, <0x110000 0x8800>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 65>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
+ status = "disabled";
+ };
+
+ can5: can@e083c000 {
+ compatible = "bosch,m_can";
+ reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 66>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>;
+ status = "disabled";
+ };
+
adc: adc@e1000000 {
compatible = "microchip,sama7g5-adc";
reg = <0xe1000000 0x200>;
--
2.17.1
next prev parent reply other threads:[~2022-02-22 11:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-22 11:39 [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Hari Prasath
2022-02-22 11:39 ` Hari Prasath [this message]
2022-02-22 11:39 ` [PATCH] 3/3] ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ek Hari Prasath
2022-02-22 20:46 ` [PATCH] 1/3] ARM: dts: at91: sama7g5: Restrict ns_sram Alexandre Belloni
2022-02-24 15:47 ` Nicolas Ferre
2022-02-24 17:50 ` Alexandre Belloni
2022-02-24 15:50 ` Nicolas Ferre
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