Re: [PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue

[Miles Chen <miles.chen@mediatek.com>]

Hi Chun-Jie,

>Power reset maybe generate unexpected signal. In order to avoid
>the glitch issue, we need to enable isolation first to guarantee the
>stable signal when power reset is triggered.
>
>Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains")
>Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
>---
>This patch is based on 5.17-rc1.
>---
> drivers/soc/mediatek/mtk-pm-domains.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
>index b762bc40f56b..0195f6c3396b 100644
>--- a/drivers/soc/mediatek/mtk-pm-domains.c
>+++ b/drivers/soc/mediatek/mtk-pm-domains.c
>@@ -272,9 +272,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> 	clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
> 
> 	/* subsys power off */
>-	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
> 	regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
> 	regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
>+	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
> 	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
> 	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
 
Does it mean that we have to do power off by:
regmap_set_bits(PWR_ISO_BIT)
regmap_clear_bits(PWR_RST_B_BIT )

and do power on by:
regmap_set_bits(PWR_RST_B_BIT)
regmap_clear_bits(PWR_ISO_BIT)

But scpsys_power_on() has the following sequence:
regmap_clear_bits(PWR_ISO_BIT)
regmap_set_bits(PWR_RST_B_BIT)

Thanks,
Miles