* [PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue
@ 2022-03-10 1:15 Chun-Jie Chen
2022-03-10 3:30 ` Chen-Yu Tsai
2022-03-10 3:59 ` Miles Chen
0 siblings, 2 replies; 5+ messages in thread
From: Chun-Jie Chen @ 2022-03-10 1:15 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream,
Project_Global_Chrome_Upstream_Group, Chun-Jie Chen
Power reset maybe generate unexpected signal. In order to avoid
the glitch issue, we need to enable isolation first to guarantee the
stable signal when power reset is triggered.
Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains")
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
This patch is based on 5.17-rc1.
---
drivers/soc/mediatek/mtk-pm-domains.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index b762bc40f56b..0195f6c3396b 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -272,9 +272,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
/* subsys power off */
- regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
+ regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
--
2.18.0
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue
2022-03-10 1:15 [PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue Chun-Jie Chen
@ 2022-03-10 3:30 ` Chen-Yu Tsai
2022-03-10 3:59 ` Miles Chen
1 sibling, 0 replies; 5+ messages in thread
From: Chen-Yu Tsai @ 2022-03-10 3:30 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, Mar 10, 2022 at 9:20 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Power reset maybe generate unexpected signal. In order to avoid
> the glitch issue, we need to enable isolation first to guarantee the
> stable signal when power reset is triggered.
>
> Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains")
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
> This patch is based on 5.17-rc1.
> ---
> drivers/soc/mediatek/mtk-pm-domains.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> index b762bc40f56b..0195f6c3396b 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -272,9 +272,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
>
> /* subsys power off */
> - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
> regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
> regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
> + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
> regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
> regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
>
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue
2022-03-10 1:15 [PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue Chun-Jie Chen
2022-03-10 3:30 ` Chen-Yu Tsai
@ 2022-03-10 3:59 ` Miles Chen
2022-03-11 2:54 ` Chun-Jie Chen
1 sibling, 1 reply; 5+ messages in thread
From: Miles Chen @ 2022-03-10 3:59 UTC (permalink / raw)
To: chun-jie.chen
Cc: Project_Global_Chrome_Upstream_Group, drinkcat, eballetbo,
linux-arm-kernel, linux-kernel, linux-mediatek, matthias.bgg,
srv_heupstream
Hi Chun-Jie,
>Power reset maybe generate unexpected signal. In order to avoid
>the glitch issue, we need to enable isolation first to guarantee the
>stable signal when power reset is triggered.
>
>Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains")
>Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
>---
>This patch is based on 5.17-rc1.
>---
> drivers/soc/mediatek/mtk-pm-domains.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
>index b762bc40f56b..0195f6c3396b 100644
>--- a/drivers/soc/mediatek/mtk-pm-domains.c
>+++ b/drivers/soc/mediatek/mtk-pm-domains.c
>@@ -272,9 +272,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
>
> /* subsys power off */
>- regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
> regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
> regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
>+ regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
> regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
> regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
Does it mean that we have to do power off by:
regmap_set_bits(PWR_ISO_BIT)
regmap_clear_bits(PWR_RST_B_BIT )
and do power on by:
regmap_set_bits(PWR_RST_B_BIT)
regmap_clear_bits(PWR_ISO_BIT)
But scpsys_power_on() has the following sequence:
regmap_clear_bits(PWR_ISO_BIT)
regmap_set_bits(PWR_RST_B_BIT)
Thanks,
Miles
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue
2022-03-10 3:59 ` Miles Chen
@ 2022-03-11 2:54 ` Chun-Jie Chen
2022-03-11 3:57 ` Miles Chen
0 siblings, 1 reply; 5+ messages in thread
From: Chun-Jie Chen @ 2022-03-11 2:54 UTC (permalink / raw)
To: Miles Chen
Cc: Project_Global_Chrome_Upstream_Group, drinkcat, eballetbo,
linux-arm-kernel, linux-kernel, linux-mediatek, matthias.bgg,
srv_heupstream
On Thu, 2022-03-10 at 11:59 +0800, Miles Chen wrote:
> Hi Chun-Jie,
>
> > Power reset maybe generate unexpected signal. In order to avoid
> > the glitch issue, we need to enable isolation first to guarantee
> > the
> > stable signal when power reset is triggered.
> >
> > Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power
> > domains")
> > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > ---
> > This patch is based on 5.17-rc1.
> > ---
> > drivers/soc/mediatek/mtk-pm-domains.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c
> > b/drivers/soc/mediatek/mtk-pm-domains.c
> > index b762bc40f56b..0195f6c3396b 100644
> > --- a/drivers/soc/mediatek/mtk-pm-domains.c
> > +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> > @@ -272,9 +272,9 @@ static int scpsys_power_off(struct
> > generic_pm_domain *genpd)
> > clk_bulk_disable_unprepare(pd->num_subsys_clks, pd-
> > >subsys_clks);
> >
> > /* subsys power off */
> > - regmap_clear_bits(scpsys->base, pd->data->ctl_offs,
> > PWR_RST_B_BIT);
> > regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
> > regmap_set_bits(scpsys->base, pd->data->ctl_offs,
> > PWR_CLK_DIS_BIT);
> > + regmap_clear_bits(scpsys->base, pd->data->ctl_offs,
> > PWR_RST_B_BIT);
> > regmap_clear_bits(scpsys->base, pd->data->ctl_offs,
> > PWR_ON_2ND_BIT);
> > regmap_clear_bits(scpsys->base, pd->data->ctl_offs,
> > PWR_ON_BIT);
>
>
> Does it mean that we have to do power off by:
> regmap_set_bits(PWR_ISO_BIT)
> regmap_clear_bits(PWR_RST_B_BIT )
>
> and do power on by:
> regmap_set_bits(PWR_RST_B_BIT)
> regmap_clear_bits(PWR_ISO_BIT)
>
> But scpsys_power_on() has the following sequence:
> regmap_clear_bits(PWR_ISO_BIT)
> regmap_set_bits(PWR_RST_B_BIT)
>
> Thanks,
> Miles
Hi Miles,
This control sequence is suggested by hardware designer,
and when PWR_RST_B from 0 -> 1, it will trigger to exit from reset
state to running state, if we still enable isolation then can't start
running normally, so we need to disable isolation first in power on
sequence.
Thanks!
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue
2022-03-11 2:54 ` Chun-Jie Chen
@ 2022-03-11 3:57 ` Miles Chen
0 siblings, 0 replies; 5+ messages in thread
From: Miles Chen @ 2022-03-11 3:57 UTC (permalink / raw)
To: chun-jie.chen
Cc: Project_Global_Chrome_Upstream_Group, drinkcat, eballetbo,
linux-arm-kernel, linux-kernel, linux-mediatek, matthias.bgg,
miles.chen, srv_heupstream
Hi Chun-Jie,
> Hi Miles,
>
> This control sequence is suggested by hardware designer,
> and when PWR_RST_B from 0 -> 1, it will trigger to exit from reset
> state to running state, if we still enable isolation then can't start
> running normally, so we need to disable isolation first in power on
> sequence.
>
Thanks for your explanation.
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Thanks,
Miles
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-03-11 3:58 UTC | newest]
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2022-03-10 1:15 [PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue Chun-Jie Chen
2022-03-10 3:30 ` Chen-Yu Tsai
2022-03-10 3:59 ` Miles Chen
2022-03-11 2:54 ` Chun-Jie Chen
2022-03-11 3:57 ` Miles Chen
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