From: Marcel Ziswiler <marcel@ziswiler.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>,
Andrejs Cainikovs <andrejs.cainikovs@toradex.com>,
Arnd Bergmann <arnd@arndb.de>, Fabio Estevam <festevam@gmail.com>,
Frank Rowand <frowand.list@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
NXP Linux Team <linux-imx@nxp.com>,
Olof Johansson <olof@lixom.net>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v1 07/10] arm64: dts: imx8mm-verdin: re-order pinctrl groups
Date: Thu, 24 Mar 2022 16:56:46 +0100 [thread overview]
Message-ID: <20220324155649.285924-8-marcel@ziswiler.com> (raw)
In-Reply-To: <20220324155649.285924-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Alphabetically re-order pinctrl groups.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
.../boot/dts/freescale/imx8mm-verdin.dtsi | 92 +++++++++----------
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 7976d055f17b..f188ac187c37 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -796,36 +796,36 @@ pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
pinctrl_ecspi2: ecspi2grp {
fsl,pins =
- <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
- <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
<MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
+ <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
+ <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
<MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
<MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
<MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
<MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
- <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>, /* CAN_1_SPI_CS_1.8V# */
- <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>; /* CAN_2_SPI_CS#_1.8V */
+ <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
};
pinctrl_fec1: fec1grp {
fsl,pins =
<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
- <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
- <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
- <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
- <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
- <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
- <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
- <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
- <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
+ <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
+ <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
+ <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
+ <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
+ <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
};
@@ -834,17 +834,17 @@ pinctrl_fec1_sleep: fec1-sleepgrp {
fsl,pins =
<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
- <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
- <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
- <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
- <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
- <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
- <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
- <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
- <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
+ <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
+ <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
+ <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
+ <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
+ <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
};
@@ -854,11 +854,11 @@ pinctrl_flexspi0: flexspi0grp {
<MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
<MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
- <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>, /* SODIMM 66 */
<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
- <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>; /* SODIMM 62 */
+ <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
+ <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
};
pinctrl_gpio1: gpio1grp {
@@ -1063,9 +1063,9 @@ pinctrl_reg_usb2_en: regusb2engrp {
pinctrl_sai2: sai2grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
- <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
<MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
+ <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
+ <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
<MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
<MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
};
@@ -1095,23 +1095,23 @@ pinctrl_tsp: tspgrp {
pinctrl_uart1: uart1grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>, /* SODIMM 149 */
- <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>; /* SODIMM 147 */
+ <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
+ <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
};
pinctrl_uart2: uart2grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>, /* SODIMM 129 */
- <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
<MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
- <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>; /* SODIMM 135 */
+ <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
+ <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
+ <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
};
pinctrl_uart3: uart3grp {
fsl,pins =
- <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
- <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
+ <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
+ <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
};
@@ -1181,35 +1181,35 @@ pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
pinctrl_usdhc2: usdhc2grp {
fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>, /* SODIMM 72 */
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>,
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>,
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
};
/*
@@ -1218,32 +1218,32 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
*/
pinctrl_usdhc3: usdhc3grp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>;
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>;
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>;
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
};
pinctrl_wdog: wdoggrp {
--
2.34.1
next prev parent reply other threads:[~2022-03-24 15:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-24 15:56 [PATCH v1 00/10] arm64: dts: imx8mm-verdin: minor updates Marcel Ziswiler
2022-03-24 15:56 ` [PATCH v1 01/10] arm64: dts: imx8mm-verdin: update regulator names Marcel Ziswiler
2022-03-24 15:56 ` [PATCH v1 02/10] arm64: dts: imx8mm-verdin: multi-line comment style Marcel Ziswiler
2022-03-24 15:56 ` [PATCH v1 03/10] arm64: dts: imx8mm-verdin: alphabetically re-order nodes Marcel Ziswiler
2022-03-24 15:56 ` [PATCH v1 04/10] arm64: dts: imx8mm-verdin: only dashes in node names Marcel Ziswiler
2022-03-24 15:56 ` [PATCH v1 05/10] arm64: dts: imx8mm-verdin: comment about i2c level shifter Marcel Ziswiler
2022-03-24 15:56 ` [PATCH v1 06/10] arm64: dts: imx8mm-verdin: update iomux configuration Marcel Ziswiler
2022-03-24 15:56 ` Marcel Ziswiler [this message]
2022-03-24 15:56 ` [PATCH v1 08/10] arm64: dts: imx8mm-verdin: capitalisation of verdin comments Marcel Ziswiler
2022-03-24 15:56 ` [PATCH v1 09/10] arm64: dts: imx8mm-verdin: note about disabled sd1 pull-ups Marcel Ziswiler
2022-03-24 15:56 ` [PATCH v1 10/10] arm64: dts: imx8mm-verdin: add sd1 sleep pinctrl Marcel Ziswiler
2022-04-10 7:46 ` [PATCH v1 00/10] arm64: dts: imx8mm-verdin: minor updates Shawn Guo
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