From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com,
like.xu.linux@gmail.com, vkuznets@redhat.com,
wei.w.wang@intel.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Like Xu <like.xu@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Kan Liang <kan.liang@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v10 04/16] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers
Date: Fri, 22 Apr 2022 03:54:57 -0400 [thread overview]
Message-ID: <20220422075509.353942-5-weijiang.yang@intel.com> (raw)
In-Reply-To: <20220422075509.353942-1-weijiang.yang@intel.com>
From: Like Xu <like.xu@linux.intel.com>
The x86_pmu.lbr_info is 0 unless explicitly initialized, so there's
no point checking x86_pmu.intel_cap.lbr_format.
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
arch/x86/events/intel/lbr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index fe1742c4ca49..4529ce448b2e 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1874,12 +1874,10 @@ void __init intel_pmu_arch_lbr_init(void)
*/
int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
{
- int lbr_fmt = x86_pmu.intel_cap.lbr_format;
-
lbr->nr = x86_pmu.lbr_nr;
lbr->from = x86_pmu.lbr_from;
lbr->to = x86_pmu.lbr_to;
- lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0;
+ lbr->info = x86_pmu.lbr_info;
return 0;
}
--
2.27.0
next prev parent reply other threads:[~2022-04-22 7:56 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-22 7:54 [PATCH v10 00/16] Introduce Architectural LBR for vPMU Yang Weijiang
2022-04-22 7:54 ` [PATCH v10 01/16] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2022-04-22 7:54 ` [PATCH v10 02/16] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2022-04-22 7:54 ` [PATCH v10 03/16] perf/x86/intel: Fix the comment about guest LBR support on KVM Yang Weijiang
2022-04-22 7:54 ` Yang Weijiang [this message]
2022-04-22 7:54 ` [PATCH v10 05/16] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2022-04-22 7:54 ` [PATCH v10 06/16] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2022-04-22 7:55 ` [PATCH v10 07/16] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2022-04-28 14:16 ` Liang, Kan
2022-04-29 3:20 ` Yang, Weijiang
2022-04-29 8:19 ` Yang, Weijiang
2022-04-22 7:55 ` [PATCH v10 08/16] KVM: x86/pmu: Refactor code to support " Yang Weijiang
2022-04-28 14:18 ` Liang, Kan
2022-04-29 5:45 ` Yang, Weijiang
2022-04-22 7:55 ` [PATCH v10 09/16] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2022-04-22 7:55 ` [PATCH v10 10/16] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2022-04-22 7:55 ` [PATCH v10 11/16] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2022-04-22 7:55 ` [PATCH v10 12/16] KVM: nVMX: Add necessary Arch LBR settings for nested VM Yang Weijiang
2022-04-22 7:55 ` [PATCH v10 13/16] KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest Yang Weijiang
2022-04-22 7:55 ` [PATCH v10 14/16] KVM: x86/vmx: Flip Arch LBREn bit on guest state change Yang Weijiang
2022-04-22 7:55 ` [PATCH v10 15/16] KVM: x86: Add Arch LBR data MSR access interface Yang Weijiang
2022-04-28 15:05 ` Liang, Kan
2022-04-29 6:34 ` Yang, Weijiang
2022-04-22 7:55 ` [PATCH v10 16/16] KVM: x86/cpuid: Advertise Arch LBR feature in CPUID Yang Weijiang
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