* [PATCH v11 1/3] dt-bindings: edac: nuvoton: add NPCM memory controller
2022-05-27 6:11 [PATCH v11 0/3] EDAC: nuvoton: Add nuvoton NPCM memory controller driver medadyoung
@ 2022-05-27 6:11 ` medadyoung
2022-05-27 6:11 ` [PATCH v11 2/3] ARM: dts: nuvoton: Add memory controller node medadyoung
2022-05-27 6:11 ` [PATCH v11 3/3] EDAC: nuvoton: Add NPCM memory controller driver medadyoung
2 siblings, 0 replies; 4+ messages in thread
From: medadyoung @ 2022-05-27 6:11 UTC (permalink / raw)
To: rric, james.morse, tony.luck, mchehab, bp, robh+dt, benjaminfair,
yuenn, venture, KWLIU, YSCHU, JJLIU0, KFTING, avifishman70,
tmaimon77, tali.perry1, ctcchien
Cc: linux-edac, linux-kernel, devicetree, openbmc
From: Medad CChien <ctcchien@nuvoton.com>
Document devicetree bindings for the Nuvoton BMC NPCM memory controller.
Signed-off-by: Medad CChien <ctcchien@nuvoton.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../edac/nuvoton,npcm-memory-controller.yaml | 62 +++++++++++++++++++
MAINTAINERS | 2 +
2 files changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml
diff --git a/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml
new file mode 100644
index 000000000000..a5c8d332d1c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/nuvoton,npcm-memory-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM Memory Controller
+
+maintainers:
+ - Medad CChien <ctcchien@nuvoton.com>
+ - Stanley Chu <yschu@nuvoton.com>
+
+description: |
+ The Nuvoton BMC SoC supports DDR4 memory with and without ECC (error
+ correction check).
+
+ The memory controller supports single bit error correction, double bit
+ error detection (in-line ECC in which a section (1/8th) of the memory
+ device used to store data is used for ECC storage).
+
+ Note, the bootloader must configure ECC mode for the memory controller.
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,npcm750-memory-controller
+ - nuvoton,npcm845-memory-controller
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ items:
+ - description: uncorrectable error interrupt
+ - description: correctable error interrupt
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: ue
+ - const: ce
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ ahb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ mc: memory-controller@f0824000 {
+ compatible = "nuvoton,npcm750-memory-controller";
+ reg = <0x0 0xf0824000 0x0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 4383949ff654..7f832e6ed4e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2367,12 +2367,14 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
S: Supported
F: Documentation/devicetree/bindings/*/*/*npcm*
F: Documentation/devicetree/bindings/*/*npcm*
+F: Documentation/devicetree/bindings/*/npcm-memory-controller.yaml
F: arch/arm/boot/dts/nuvoton-npcm*
F: arch/arm/mach-npcm/
F: drivers/*/*npcm*
F: drivers/*/*/*npcm*
F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
+
ARM/NUVOTON WPCM450 ARCHITECTURE
M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v11 2/3] ARM: dts: nuvoton: Add memory controller node
2022-05-27 6:11 [PATCH v11 0/3] EDAC: nuvoton: Add nuvoton NPCM memory controller driver medadyoung
2022-05-27 6:11 ` [PATCH v11 1/3] dt-bindings: edac: nuvoton: add NPCM memory controller medadyoung
@ 2022-05-27 6:11 ` medadyoung
2022-05-27 6:11 ` [PATCH v11 3/3] EDAC: nuvoton: Add NPCM memory controller driver medadyoung
2 siblings, 0 replies; 4+ messages in thread
From: medadyoung @ 2022-05-27 6:11 UTC (permalink / raw)
To: rric, james.morse, tony.luck, mchehab, bp, robh+dt, benjaminfair,
yuenn, venture, KWLIU, YSCHU, JJLIU0, KFTING, avifishman70,
tmaimon77, tali.perry1, ctcchien
Cc: linux-edac, linux-kernel, devicetree, openbmc
From: Medad CChien <ctcchien@nuvoton.com>
ECC must be configured in the BootBlock header.
Then, you can read error counts via the EDAC kernel framework.
Signed-off-by: Medad CChien <ctcchien@nuvoton.com>
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 3696980a3da1..ba542b26941e 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -106,6 +106,13 @@
interrupt-parent = <&gic>;
ranges;
+ mc: memory-controller@f0824000 {
+ compatible = "nuvoton,npcm750-memory-controller";
+ reg = <0x0 0xf0824000 0x0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
rstc: rstc@f0801000 {
compatible = "nuvoton,npcm750-reset";
reg = <0xf0801000 0x70>;
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v11 3/3] EDAC: nuvoton: Add NPCM memory controller driver
2022-05-27 6:11 [PATCH v11 0/3] EDAC: nuvoton: Add nuvoton NPCM memory controller driver medadyoung
2022-05-27 6:11 ` [PATCH v11 1/3] dt-bindings: edac: nuvoton: add NPCM memory controller medadyoung
2022-05-27 6:11 ` [PATCH v11 2/3] ARM: dts: nuvoton: Add memory controller node medadyoung
@ 2022-05-27 6:11 ` medadyoung
2 siblings, 0 replies; 4+ messages in thread
From: medadyoung @ 2022-05-27 6:11 UTC (permalink / raw)
To: rric, james.morse, tony.luck, mchehab, bp, robh+dt, benjaminfair,
yuenn, venture, KWLIU, YSCHU, JJLIU0, KFTING, avifishman70,
tmaimon77, tali.perry1, ctcchien
Cc: linux-edac, linux-kernel, devicetree, openbmc
From: Medad CChien <ctcchien@nuvoton.com>
Add memory controller support for Nuvoton NPCM SoC.
Note:
you can force an ecc event by writing a string to edac sysfs node
and remember to define CONFIG_EDAC_DEBUG to enable this feature
example: force a correctable event on checkcode bit 0
echo "CE checkcode 0" to below path
/sys/devices/system/edac/mc/mc0/forced_ecc_error
Datasheet:
Cadence DDR Controller Register Reference Manual For DDR4 Memories
Chapter 2: Detailed Register Map
Signed-off-by: Medad CChien <ctcchien@nuvoton.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f832e6ed4e5..8919fb83f485 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2372,9 +2372,9 @@ F: arch/arm/boot/dts/nuvoton-npcm*
F: arch/arm/mach-npcm/
F: drivers/*/*npcm*
F: drivers/*/*/*npcm*
+F: drivers/edac/npcm_edac.c b/drivers/edac/npcm_edac.c
F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
-
ARM/NUVOTON WPCM450 ARCHITECTURE
M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread