* [PATCH] mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R
@ 2022-06-30 9:09 Eugen Hristev
2022-07-02 16:51 ` Adrian Hunter
2022-07-12 11:09 ` Ulf Hansson
0 siblings, 2 replies; 3+ messages in thread
From: Eugen Hristev @ 2022-06-30 9:09 UTC (permalink / raw)
To: ulf.hansson
Cc: adrian.hunter, linux-mmc, linux-arm-kernel, linux-kernel,
Eugen Hristev, Karl Olsen
In set_uhs_signaling, the DDR bit is being set by fully writing the MC1R
register.
This can lead to accidental erase of certain bits in this register.
Avoid this by doing a read-modify-write operation.
Fixes: d0918764c17b ("mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Karl Olsen <karl@micro-technic.com>
---
drivers/mmc/host/sdhci-of-at91.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
index 10fb4cb2c731..cd0134580a90 100644
--- a/drivers/mmc/host/sdhci-of-at91.c
+++ b/drivers/mmc/host/sdhci-of-at91.c
@@ -100,8 +100,13 @@ static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
unsigned int timing)
{
- if (timing == MMC_TIMING_MMC_DDR52)
- sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
+ u8 mc1r;
+
+ if (timing == MMC_TIMING_MMC_DDR52) {
+ mc1r = sdhci_readb(host, SDMMC_MC1R);
+ mc1r |= SDMMC_MC1R_DDR;
+ sdhci_writeb(host, mc1r, SDMMC_MC1R);
+ }
sdhci_set_uhs_signaling(host, timing);
}
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R
2022-06-30 9:09 [PATCH] mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R Eugen Hristev
@ 2022-07-02 16:51 ` Adrian Hunter
2022-07-12 11:09 ` Ulf Hansson
1 sibling, 0 replies; 3+ messages in thread
From: Adrian Hunter @ 2022-07-02 16:51 UTC (permalink / raw)
To: Eugen Hristev, ulf.hansson
Cc: linux-mmc, linux-arm-kernel, linux-kernel, Karl Olsen
On 30/06/22 12:09, Eugen Hristev wrote:
> In set_uhs_signaling, the DDR bit is being set by fully writing the MC1R
> register.
> This can lead to accidental erase of certain bits in this register.
> Avoid this by doing a read-modify-write operation.
>
> Fixes: d0918764c17b ("mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection")
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
> Tested-by: Karl Olsen <karl@micro-technic.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/sdhci-of-at91.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
> index 10fb4cb2c731..cd0134580a90 100644
> --- a/drivers/mmc/host/sdhci-of-at91.c
> +++ b/drivers/mmc/host/sdhci-of-at91.c
> @@ -100,8 +100,13 @@ static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
> static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
> unsigned int timing)
> {
> - if (timing == MMC_TIMING_MMC_DDR52)
> - sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
> + u8 mc1r;
> +
> + if (timing == MMC_TIMING_MMC_DDR52) {
> + mc1r = sdhci_readb(host, SDMMC_MC1R);
> + mc1r |= SDMMC_MC1R_DDR;
> + sdhci_writeb(host, mc1r, SDMMC_MC1R);
> + }
> sdhci_set_uhs_signaling(host, timing);
> }
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R
2022-06-30 9:09 [PATCH] mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R Eugen Hristev
2022-07-02 16:51 ` Adrian Hunter
@ 2022-07-12 11:09 ` Ulf Hansson
1 sibling, 0 replies; 3+ messages in thread
From: Ulf Hansson @ 2022-07-12 11:09 UTC (permalink / raw)
To: Eugen Hristev
Cc: adrian.hunter, linux-mmc, linux-arm-kernel, linux-kernel, Karl Olsen
On Thu, 30 Jun 2022 at 11:09, Eugen Hristev <eugen.hristev@microchip.com> wrote:
>
> In set_uhs_signaling, the DDR bit is being set by fully writing the MC1R
> register.
> This can lead to accidental erase of certain bits in this register.
> Avoid this by doing a read-modify-write operation.
>
> Fixes: d0918764c17b ("mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection")
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
> Tested-by: Karl Olsen <karl@micro-technic.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-of-at91.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
> index 10fb4cb2c731..cd0134580a90 100644
> --- a/drivers/mmc/host/sdhci-of-at91.c
> +++ b/drivers/mmc/host/sdhci-of-at91.c
> @@ -100,8 +100,13 @@ static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
> static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
> unsigned int timing)
> {
> - if (timing == MMC_TIMING_MMC_DDR52)
> - sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
> + u8 mc1r;
> +
> + if (timing == MMC_TIMING_MMC_DDR52) {
> + mc1r = sdhci_readb(host, SDMMC_MC1R);
> + mc1r |= SDMMC_MC1R_DDR;
> + sdhci_writeb(host, mc1r, SDMMC_MC1R);
> + }
> sdhci_set_uhs_signaling(host, timing);
> }
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-07-12 11:10 UTC | newest]
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2022-06-30 9:09 [PATCH] mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R Eugen Hristev
2022-07-02 16:51 ` Adrian Hunter
2022-07-12 11:09 ` Ulf Hansson
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