From: Conor Dooley <mail@conchuod.ie>
To: Daire McNamara <daire.mcnamara@microchip.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greentime Hu <greentime.hu@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties
Date: Thu, 11 Aug 2022 21:33:05 +0100 [thread overview]
Message-ID: <20220811203306.179744-3-mail@conchuod.ie> (raw)
In-Reply-To: <20220811203306.179744-1-mail@conchuod.ie>
From: Conor Dooley <conor.dooley@microchip.com>
Upgrading dt-schema to v2022.08 reveals unevaluatedProperties issues
that were not previously visible, such as the missing clocks and
clock-names properties for PolarFire SoC's PCI controller:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected)
From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
The clocks are required to enable interfaces between the FPGA fabric
and the core complex, so add them to the binding.
Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/pci/microchip,pcie-host.yaml | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index edb4f81253c8..2a2166f09e2c 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -25,6 +25,31 @@ properties:
- const: cfg
- const: apb
+ clocks:
+ description:
+ Fabric Interface Controllers, FICs, are the interface between the FPGA
+ fabric and the core complex on PolarFire SoC. The FICs require two clocks,
+ one from each side of the interface. The "FIC clocks" described by this
+ property are on the core complex side & communication through a FIC is not
+ possible unless it's corresponding clock is enabled. A clock must be
+ enabled for each of the interfaces the root port is connected through.
+ minItems: 1
+ items:
+ - description: FIC0's clock
+ - description: FIC1's clock
+ - description: FIC2's clock
+ - description: FIC3's clock
+
+ clock-names:
+ items:
+ enum:
+ - fic0
+ - fic1
+ - fic2
+ - fic3
+ minItems: 1
+ maxItems: 4
+
interrupts:
minItems: 1
items:
--
2.37.1
next prev parent reply other threads:[~2022-08-11 20:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-11 20:33 [PATCH 0/4] Fix RISC-V/PCI dt-schema issues with dt-schema v2022.08 Conor Dooley
2022-08-11 20:33 ` [PATCH 1/4] dt-bindings: PCI: fu740-pci: fix missing clock-names Conor Dooley
2022-08-12 7:34 ` Krzysztof Kozlowski
2022-08-12 7:57 ` Conor.Dooley
2022-08-11 20:33 ` Conor Dooley [this message]
2022-08-12 7:35 ` [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties Krzysztof Kozlowski
2022-08-12 8:00 ` Krzysztof Kozlowski
2022-08-12 8:09 ` Conor.Dooley
2022-08-14 13:47 ` Conor.Dooley
2022-08-16 7:25 ` Krzysztof Kozlowski
2022-08-11 20:33 ` [PATCH 3/4] dt-bindings: PCI: microchip,pcie-host: fix incorrect child node name Conor Dooley
2022-08-12 7:42 ` Krzysztof Kozlowski
2022-08-12 7:55 ` Conor.Dooley
2022-08-12 10:07 ` Krzysztof Kozlowski
2022-08-11 20:33 ` [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property Conor Dooley
2022-08-12 7:52 ` Krzysztof Kozlowski
2022-08-12 8:20 ` Conor.Dooley
2022-08-16 17:16 ` Rob Herring
2022-08-16 17:59 ` Conor.Dooley
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