From: Conor Dooley <mail@conchuod.ie>
To: Daire McNamara <daire.mcnamara@microchip.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greentime Hu <greentime.hu@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property
Date: Thu, 11 Aug 2022 21:33:07 +0100 [thread overview]
Message-ID: <20220811203306.179744-5-mail@conchuod.ie> (raw)
In-Reply-To: <20220811203306.179744-1-mail@conchuod.ie>
From: Conor Dooley <conor.dooley@microchip.com>
When the PCI controller node was added to the PolarFire SoC dtsi,
dt-schema was not able to detect the presence of some undocumented
properties due to how it handled unevaluatedProperties. v2022.08
introduces better validation, producing the following error:
arch/riscv/boot/dts/microchip/mpfs-polarberry.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'microchip,axi-m-atr0' were unexpected)
From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
I feel like there's a pretty good chance that this is not the way this
should have been done and the property should be marked as deprecated
but I don't know enough about PCI to answer that.
---
.../devicetree/bindings/pci/microchip,pcie-host.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 9b123bcd034c..9ac34b33c4b2 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -71,6 +71,17 @@ properties:
msi-parent:
description: MSI controller the device is capable of using.
+ microchip,axi-m-atr0:
+ description: |
+ Depending on the FPGA bitstream, the AXIM address translation table in the
+ PCIe controllers bridge layer may need to be configured. Use this property
+ to set the address offset. For more information, see Section 1.3.3,
+ "PCIe/AXI4 Address Translation" of the PolarFire SoC PCIe User Guide:
+ https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 2
+ maxItems: 2
+
legacy-interrupt-controller:
type: object
properties:
--
2.37.1
next prev parent reply other threads:[~2022-08-11 20:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-11 20:33 [PATCH 0/4] Fix RISC-V/PCI dt-schema issues with dt-schema v2022.08 Conor Dooley
2022-08-11 20:33 ` [PATCH 1/4] dt-bindings: PCI: fu740-pci: fix missing clock-names Conor Dooley
2022-08-12 7:34 ` Krzysztof Kozlowski
2022-08-12 7:57 ` Conor.Dooley
2022-08-11 20:33 ` [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties Conor Dooley
2022-08-12 7:35 ` Krzysztof Kozlowski
2022-08-12 8:00 ` Krzysztof Kozlowski
2022-08-12 8:09 ` Conor.Dooley
2022-08-14 13:47 ` Conor.Dooley
2022-08-16 7:25 ` Krzysztof Kozlowski
2022-08-11 20:33 ` [PATCH 3/4] dt-bindings: PCI: microchip,pcie-host: fix incorrect child node name Conor Dooley
2022-08-12 7:42 ` Krzysztof Kozlowski
2022-08-12 7:55 ` Conor.Dooley
2022-08-12 10:07 ` Krzysztof Kozlowski
2022-08-11 20:33 ` Conor Dooley [this message]
2022-08-12 7:52 ` [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property Krzysztof Kozlowski
2022-08-12 8:20 ` Conor.Dooley
2022-08-16 17:16 ` Rob Herring
2022-08-16 17:59 ` Conor.Dooley
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