From: Juergen Gross <jgross@suse.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org
Cc: Juergen Gross <jgross@suse.com>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
xen-devel@lists.xenproject.org, Jan Beulich <jbeulich@suse.com>
Subject: [PATCH v3 2/4] xen/pv: fix vendor checks for pmu emulation
Date: Wed, 5 Oct 2022 13:03:00 +0200 [thread overview]
Message-ID: <20221005110302.13455-3-jgross@suse.com> (raw)
In-Reply-To: <20221005110302.13455-1-jgross@suse.com>
The CPU vendor checks for pmu emulation are rather limited today, as
the assumption seems to be that only Intel and AMD are existing and/or
supported vendors.
Fix that by handling Centaur and Zhaoxin CPUs the same way as Intel,
and Hygon the same way as AMD.
While at it fix the return type of is_intel_pmu_msr().
Suggested-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
V3:
- new patch
---
arch/x86/xen/pmu.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
index 0f98cb1077e3..68aff1382872 100644
--- a/arch/x86/xen/pmu.c
+++ b/arch/x86/xen/pmu.c
@@ -131,7 +131,8 @@ static inline uint32_t get_fam15h_addr(u32 addr)
static inline bool is_amd_pmu_msr(unsigned int msr)
{
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
return false;
if ((msr >= MSR_F15H_PERF_CTL &&
@@ -143,11 +144,13 @@ static inline bool is_amd_pmu_msr(unsigned int msr)
return false;
}
-static int is_intel_pmu_msr(u32 msr_index, int *type, int *index)
+static bool is_intel_pmu_msr(u32 msr_index, int *type, int *index)
{
u32 msr_index_pmc;
- if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return false;
switch (msr_index) {
--
2.35.3
next prev parent reply other threads:[~2022-10-05 11:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-05 11:02 [PATCH v3 0/4] xen/pv: sanitize xen pv guest msr accesses Juergen Gross
2022-10-05 11:02 ` [PATCH v3 1/4] xen/pv: add fault recovery control to pmu " Juergen Gross
2022-10-05 11:58 ` Jan Beulich
2022-10-05 11:03 ` Juergen Gross [this message]
2022-10-05 11:59 ` [PATCH v3 2/4] xen/pv: fix vendor checks for pmu emulation Jan Beulich
2022-10-05 11:03 ` [PATCH v3 3/4] xen/pv: refactor msr access functions to support safe and unsafe accesses Juergen Gross
2022-10-05 11:03 ` [PATCH v3 4/4] xen/pv: support selecting safe/unsafe msr accesses Juergen Gross
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