From: Jan Beulich <jbeulich@suse.com>
To: Juergen Gross <jgross@suse.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org,
x86@kernel.org
Subject: Re: [PATCH v3 2/4] xen/pv: fix vendor checks for pmu emulation
Date: Wed, 5 Oct 2022 13:59:03 +0200 [thread overview]
Message-ID: <ed377c8c-95c3-8386-cfa2-51ae9b8add67@suse.com> (raw)
In-Reply-To: <20221005110302.13455-3-jgross@suse.com>
On 05.10.2022 13:03, Juergen Gross wrote:
> The CPU vendor checks for pmu emulation are rather limited today, as
> the assumption seems to be that only Intel and AMD are existing and/or
> supported vendors.
>
> Fix that by handling Centaur and Zhaoxin CPUs the same way as Intel,
> and Hygon the same way as AMD.
>
> While at it fix the return type of is_intel_pmu_msr().
>
> Suggested-by: Jan Beulich <jbeulich@suse.com>
> Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
next prev parent reply other threads:[~2022-10-05 11:59 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-05 11:02 [PATCH v3 0/4] xen/pv: sanitize xen pv guest msr accesses Juergen Gross
2022-10-05 11:02 ` [PATCH v3 1/4] xen/pv: add fault recovery control to pmu " Juergen Gross
2022-10-05 11:58 ` Jan Beulich
2022-10-05 11:03 ` [PATCH v3 2/4] xen/pv: fix vendor checks for pmu emulation Juergen Gross
2022-10-05 11:59 ` Jan Beulich [this message]
2022-10-05 11:03 ` [PATCH v3 3/4] xen/pv: refactor msr access functions to support safe and unsafe accesses Juergen Gross
2022-10-05 11:03 ` [PATCH v3 4/4] xen/pv: support selecting safe/unsafe msr accesses Juergen Gross
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