From: Stephen Boyd <sboyd@kernel.org>
To: Rahul Tanwar <rtanwar@maxlinear.com>,
linux-clk@vger.kernel.org, mturquette@baylibre.com,
yzhu@maxlinear.com
Cc: linux-kernel@vger.kernel.org, linux-lgm-soc@maxlinear.com,
Rahul Tanwar <rtanwar@maxlinear.com>
Subject: Re: [PATCH v4 4/4] clk: mxl: Fix a clk entry by adding relevant flags
Date: Mon, 17 Oct 2022 15:29:07 -0700 [thread overview]
Message-ID: <20221017222909.A1D51C433D7@smtp.kernel.org> (raw)
In-Reply-To: <a4770e7225f8a0c03c8ab2ba80434a4e8e9afb17.1665642720.git.rtanwar@maxlinear.com>
Quoting Rahul Tanwar (2022-10-12 23:48:33)
> One of the clock entry "dcl" clk has some HW limitations. One is that
> its rate can only by changed by changing its parent clk's rate & two
> is that HW does not support enable/disable for this clk.
>
> Handle above two limitations by adding relevant flags. Add standard
> flag CLK_SET_RATE_PARENT to handle rate change and add driver internal
> flag DIV_CLK_NO_MASK to handle enable/disable.
>
> Fixes: d058fd9e8984c ("clk: intel: Add CGU clock driver for a new SoC")
> Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
> Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
> ---
Applied to clk-next
prev parent reply other threads:[~2022-10-17 22:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 6:48 [PATCH v4 0/4] Modify MxL's CGU clk driver to make it secure boot compatible Rahul Tanwar
2022-10-13 6:48 ` [PATCH v4 1/4] clk: mxl: Switch from direct readl/writel based IO to regmap based IO Rahul Tanwar
2022-10-17 22:28 ` Stephen Boyd
2022-10-13 6:48 ` [PATCH v4 2/4] clk: mxl: Remove redundant spinlocks Rahul Tanwar
2022-10-17 22:28 ` Stephen Boyd
2022-10-13 6:48 ` [PATCH v4 3/4] clk: mxl: Add option to override gate clks Rahul Tanwar
2022-10-17 22:28 ` Stephen Boyd
2022-10-13 6:48 ` [PATCH v4 4/4] clk: mxl: Fix a clk entry by adding relevant flags Rahul Tanwar
2022-10-17 22:29 ` Stephen Boyd [this message]
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