From: Eliav Farber <farbere@amazon.com>
To: <tudor.ambarus@microchip.com>, <pratyush@kernel.org>,
<michael@walle.cc>, <miquel.raynal@bootlin.com>, <richard@nod.at>,
<vigneshr@ti.com>, <linux-mtd@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <talel@amazon.com>, <jonnyc@amazon.com>, <hhhawa@amazon.com>,
<hanochu@amazon.com>, <farbere@amazon.com>, <itamark@amazon.com>,
<shellykz@amazon.com>, <amitlavi@amazon.com>, <dkl@amazon.com>
Subject: [PATCH] mtd: spi-nor: micron-st: Enable locking for n25q256ax1
Date: Tue, 18 Oct 2022 07:22:54 +0000 [thread overview]
Message-ID: <20221018072254.21606-1-farbere@amazon.com> (raw)
n25q256ax1 [1] uses the 4 bit Block Protection scheme and supports
Top/Bottom protection via the BP and TB bits of the Status Register.
BP3 is located in bit 6 of the Status Register.
Tested on n25q256ax1.
[1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf
Signed-off-by: Eliav Farber <farbere@amazon.com>
---
drivers/mtd/spi-nor/micron-st.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3c9681a3f7a3..7cf5fbb28f99 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -206,6 +206,8 @@ static const struct flash_info st_nor_parts[] = {
MFR_FLAGS(USE_FSR)
},
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
+ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
MFR_FLAGS(USE_FSR)
},
--
2.37.1
next reply other threads:[~2022-10-18 7:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-18 7:22 Eliav Farber [this message]
2022-10-18 7:45 ` Michael Walle
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