From: Michael Walle <michael@walle.cc>
To: Eliav Farber <farbere@amazon.com>
Cc: tudor.ambarus@microchip.com, pratyush@kernel.org,
miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
talel@amazon.com, jonnyc@amazon.com, hhhawa@amazon.com,
hanochu@amazon.com, itamark@amazon.com, shellykz@amazon.com,
amitlavi@amazon.com, dkl@amazon.com
Subject: Re: [PATCH] mtd: spi-nor: micron-st: Enable locking for n25q256ax1
Date: Tue, 18 Oct 2022 09:45:34 +0200 [thread overview]
Message-ID: <bb7040f60b86b1f028fc6a40f6221ca6@walle.cc> (raw)
In-Reply-To: <20221018072254.21606-1-farbere@amazon.com>
Hi,
Am 2022-10-18 09:22, schrieb Eliav Farber:
> n25q256ax1 [1] uses the 4 bit Block Protection scheme and supports
> Top/Bottom protection via the BP and TB bits of the Status Register.
> BP3 is located in bit 6 of the Status Register.
> Tested on n25q256ax1.
>
> [1]
> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf
>
> Signed-off-by: Eliav Farber <farbere@amazon.com>
Looks good. But could you please dump the SFDP tables as
described in [1].
-michael
[1]
https://lore.kernel.org/linux-mtd/4304e19f3399a0a6e856119d01ccabe0@walle.cc/
prev parent reply other threads:[~2022-10-18 7:45 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-18 7:22 Eliav Farber
2022-10-18 7:45 ` Michael Walle [this message]
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