* [PATCH 1/9] arm64: dts: mediatek: mt8186: Add MTU3 nodes
2023-01-11 12:37 [PATCH 0/9] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
@ 2023-01-11 12:37 ` Allen-KH Cheng
2023-01-12 11:47 ` Chen-Yu Tsai
2023-01-11 12:37 ` [PATCH 2/9] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi Allen-KH Cheng
` (7 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Allen-KH Cheng @ 2023-01-11 12:37 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, hsinyi,
Allen-KH Cheng
Add MTU3 nodes for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 75 ++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c0a3afd55eaf..3d88480913eb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -908,6 +908,43 @@
status = "disabled";
};
+ ssusb0: usb@11201000 {
+ compatible = "mediatek,mt8186-mtu3",
+ "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2dff>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
+ <&infracfg_ao CLK_INFRA_AO_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host0: usb@11200000 {
+ compatible = "mediatek,mt8186-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
+ <&infracfg_ao CLK_INFRA_AO_ICUSB>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-wakeup = <&pericfg 0x420 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+
mmc0: mmc@11230000 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
@@ -939,6 +976,44 @@
status = "disabled";
};
+ ssusb1: usb@11281000 {
+ compatible = "mediatek,mt8186-mtu3",
+ "mediatek,mtu3";
+ reg = <0 0x11281000 0 0x2dff>,
+ <0 0x11283e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
+ <&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>,
+ <&u3port1 PHY_TYPE_USB3>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host1: usb@11280000 {
+ compatible = "mediatek,mt8186-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11280000 0 0x1000>;
+ reg-names = "mac";
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
+ <&clk26m>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-wakeup = <&pericfg 0x424 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+
u3phy0: t-phy@11c80000 {
compatible = "mediatek,mt8186-tphy",
"mediatek,generic-tphy-v2";
--
2.18.0
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 1/9] arm64: dts: mediatek: mt8186: Add MTU3 nodes
2023-01-11 12:37 ` [PATCH 1/9] arm64: dts: mediatek: mt8186: Add MTU3 nodes Allen-KH Cheng
@ 2023-01-12 11:47 ` Chen-Yu Tsai
0 siblings, 0 replies; 15+ messages in thread
From: Chen-Yu Tsai @ 2023-01-12 11:47 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel, devicetree,
linux-kernel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, hsinyi, linux-arm-kernel
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add MTU3 nodes for MT8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/9] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi
2023-01-11 12:37 [PATCH 0/9] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
2023-01-11 12:37 ` [PATCH 1/9] arm64: dts: mediatek: mt8186: Add MTU3 nodes Allen-KH Cheng
@ 2023-01-11 12:37 ` Allen-KH Cheng
2023-01-13 19:17 ` Rob Herring
2023-01-11 12:37 ` [PATCH 3/9] arm64: dts: mediatek: mt8186: Add SPMI node Allen-KH Cheng
` (6 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Allen-KH Cheng @ 2023-01-11 12:37 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, hsinyi,
Allen-KH Cheng
The mt8186-spmi is used as compatible with mt8195-spmi on the MT8186,
document this situation.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
.../devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
index abcbbe13723f..e4f465abcfe9 100644
--- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
+++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
@@ -18,9 +18,14 @@ allOf:
properties:
compatible:
- enum:
- - mediatek,mt6873-spmi
- - mediatek,mt8195-spmi
+ oneOf:
+ - enum:
+ - mediatek,mt6873-spmi
+ - mediatek,mt8195-spmi
+ - items:
+ - enum:
+ - mediatek,mt8186-spmi
+ - const: mediatek,mt8195-spmi
reg:
maxItems: 2
--
2.18.0
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 2/9] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi
2023-01-11 12:37 ` [PATCH 2/9] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi Allen-KH Cheng
@ 2023-01-13 19:17 ` Rob Herring
0 siblings, 0 replies; 15+ messages in thread
From: Rob Herring @ 2023-01-13 19:17 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: dri-devel, David Airlie, Stephen Boyd,
Project_Global_Chrome_Upstream_Group, Krzysztof Kozlowski,
hsinyi, AngeloGioacchino Del Regno, Rob Herring, devicetree,
linux-mediatek, Daniel Vetter, Chun-Kuang Hu, Matthias Brugger,
linux-arm-kernel, Philipp Zabel, linux-kernel
On Wed, 11 Jan 2023 20:37:04 +0800, Allen-KH Cheng wrote:
> The mt8186-spmi is used as compatible with mt8195-spmi on the MT8186,
> document this situation.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> .../devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/9] arm64: dts: mediatek: mt8186: Add SPMI node
2023-01-11 12:37 [PATCH 0/9] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
2023-01-11 12:37 ` [PATCH 1/9] arm64: dts: mediatek: mt8186: Add MTU3 nodes Allen-KH Cheng
2023-01-11 12:37 ` [PATCH 2/9] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi Allen-KH Cheng
@ 2023-01-11 12:37 ` Allen-KH Cheng
2023-01-11 12:37 ` [PATCH 4/9] arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes Allen-KH Cheng
` (5 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Allen-KH Cheng @ 2023-01-11 12:37 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, hsinyi,
Allen-KH Cheng
Add SPMI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 3d88480913eb..a8ff984f1192 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -605,6 +605,25 @@
clock-names = "spi", "wrap";
};
+ spmi: spmi@10015000 {
+ compatible = "mediatek,mt8186-spmi",
+ "mediatek,mt8195-spmi";
+ reg = <0 0x10015000 0 0x000e00>,
+ <0 0x1001B000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_MST>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8186-timer",
"mediatek,mt6765-timer";
--
2.18.0
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 4/9] arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes
2023-01-11 12:37 [PATCH 0/9] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
` (2 preceding siblings ...)
2023-01-11 12:37 ` [PATCH 3/9] arm64: dts: mediatek: mt8186: Add SPMI node Allen-KH Cheng
@ 2023-01-11 12:37 ` Allen-KH Cheng
2023-01-11 12:37 ` [PATCH 5/9] arm64: dts: mediatek: mt8186: Add ADSP node Allen-KH Cheng
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Allen-KH Cheng @ 2023-01-11 12:37 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, hsinyi,
Allen-KH Cheng
Add ADSP mailbox node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a8ff984f1192..a0b7dacc10cd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -640,6 +640,20 @@
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ adsp_mailbox0: mailbox@10686000 {
+ compatible = "mediatek,mt8186-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10686100 0 0x1000>;
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ adsp_mailbox1: mailbox@10687000 {
+ compatible = "mediatek,mt8186-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10687100 0 0x1000>;
+ interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
nor_flash: spi@11000000 {
compatible = "mediatek,mt8186-nor";
reg = <0 0x11000000 0 0x1000>;
--
2.18.0
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 5/9] arm64: dts: mediatek: mt8186: Add ADSP node
2023-01-11 12:37 [PATCH 0/9] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
` (3 preceding siblings ...)
2023-01-11 12:37 ` [PATCH 4/9] arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes Allen-KH Cheng
@ 2023-01-11 12:37 ` Allen-KH Cheng
2023-01-11 12:37 ` [PATCH 6/9] arm64: dts: mediatek: mt8186: Add audio controller node Allen-KH Cheng
` (3 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Allen-KH Cheng @ 2023-01-11 12:37 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, hsinyi,
Allen-KH Cheng
Add ADSP node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a0b7dacc10cd..2700c830316f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -640,6 +640,26 @@
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ adsp: adsp@10680000 {
+ compatible = "mediatek,mt8186-dsp";
+ reg = <0 0x10680000 0 0x2000>,
+ <0 0x10800000 0 0x100000>,
+ <0 0x1068b000 0 0x100>,
+ <0 0x1068f000 0 0x1000>;
+ reg-names = "cfg", "sram", "sec", "bus";
+ clocks = <&topckgen CLK_TOP_AUDIODSP>,
+ <&topckgen CLK_TOP_ADSP_BUS>;
+ clock-names = "audiodsp",
+ "adsp_bus";
+ assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
+ <&topckgen CLK_TOP_ADSP_BUS>;
+ assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
+ mbox-names = "rx", "tx";
+ mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
+ status = "disabled";
+ };
+
adsp_mailbox0: mailbox@10686000 {
compatible = "mediatek,mt8186-adsp-mbox";
#mbox-cells = <0>;
--
2.18.0
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 6/9] arm64: dts: mediatek: mt8186: Add audio controller node
2023-01-11 12:37 [PATCH 0/9] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
` (4 preceding siblings ...)
2023-01-11 12:37 ` [PATCH 5/9] arm64: dts: mediatek: mt8186: Add ADSP node Allen-KH Cheng
@ 2023-01-11 12:37 ` Allen-KH Cheng
2023-01-11 12:37 ` [PATCH 7/9] arm64: dts: mediatek: mt8186: Add DPI node Allen-KH Cheng
` (2 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Allen-KH Cheng @ 2023-01-11 12:37 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, hsinyi,
Allen-KH Cheng
Add audio controller node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 62 ++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 2700c830316f..c52f9be1e750 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -998,6 +998,68 @@
};
};
+ afe: audio-controller@11210000 {
+ compatible = "mediatek,mt8186-sound";
+ reg = <0 0x11210000 0 0x2000>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
+ <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_AUDIO>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&topckgen CLK_TOP_MAINPLL_D2_D4>,
+ <&topckgen CLK_TOP_AUD_1>,
+ <&apmixedsys CLK_APMIXED_APLL1>,
+ <&topckgen CLK_TOP_AUD_2>,
+ <&apmixedsys CLK_APMIXED_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1>,
+ <&topckgen CLK_TOP_APLL1_D8>,
+ <&topckgen CLK_TOP_AUD_ENGEN2>,
+ <&topckgen CLK_TOP_APLL2_D8>,
+ <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV0>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV1>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV2>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV4>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
+ <&topckgen CLK_TOP_AUDIO_H>,
+ <&clk26m>;
+ clock-names = "aud_infra_clk",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d2_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d8",
+ "top_mux_aud_eng2",
+ "top_apll2_d8",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s4_m_sel",
+ "top_tdm_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div4",
+ "top_apll12_div_tdm",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg_ao>;
+ mediatek,topckgen = <&topckgen>;
+ resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
+ reset-names = "audiosys";
+ status = "disabled";
+ };
+
mmc0: mmc@11230000 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
--
2.18.0
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 7/9] arm64: dts: mediatek: mt8186: Add DPI node
2023-01-11 12:37 [PATCH 0/9] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
` (5 preceding siblings ...)
2023-01-11 12:37 ` [PATCH 6/9] arm64: dts: mediatek: mt8186: Add audio controller node Allen-KH Cheng
@ 2023-01-11 12:37 ` Allen-KH Cheng
2023-01-12 11:48 ` Chen-Yu Tsai
2023-01-11 12:37 ` [PATCH 8/9] dt-bindings: display: mediatek: Fix the fallback for mediatek,mt8186-disp-ccorr Allen-KH Cheng
2023-01-11 12:37 ` [PATCH 9/9] arm64: dts: mediatek: mt8186: Add display nodes Allen-KH Cheng
8 siblings, 1 reply; 15+ messages in thread
From: Allen-KH Cheng @ 2023-01-11 12:37 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, hsinyi,
Allen-KH Cheng
Add DPI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c52f9be1e750..eab30ab01572 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1230,6 +1230,23 @@
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
};
+ dpi0: dpi@1400a000 {
+ compatible = "mediatek,mt8186-dpi";
+ reg = <0 0x1400a000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_DPI>,
+ <&mmsys CLK_MM_DISP_DPI>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ assigned-clocks = <&topckgen CLK_TOP_DPI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
+ status = "disabled";
+
+ port {
+ dpi_out: endpoint { };
+ };
+ };
+
dsi0: dsi@14013000 {
compatible = "mediatek,mt8186-dsi";
reg = <0 0x14013000 0 0x1000>;
--
2.18.0
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 7/9] arm64: dts: mediatek: mt8186: Add DPI node
2023-01-11 12:37 ` [PATCH 7/9] arm64: dts: mediatek: mt8186: Add DPI node Allen-KH Cheng
@ 2023-01-12 11:48 ` Chen-Yu Tsai
0 siblings, 0 replies; 15+ messages in thread
From: Chen-Yu Tsai @ 2023-01-12 11:48 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel, devicetree,
linux-kernel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, hsinyi, linux-arm-kernel
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add DPI node for MT8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index c52f9be1e750..eab30ab01572 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -1230,6 +1230,23 @@
> power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> };
>
> + dpi0: dpi@1400a000 {
You could drop the trailing 0 in the label, since there is only one
instance.
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> + compatible = "mediatek,mt8186-dpi";
> + reg = <0 0x1400a000 0 0x1000>;
> + clocks = <&topckgen CLK_TOP_DPI>,
> + <&mmsys CLK_MM_DISP_DPI>,
> + <&apmixedsys CLK_APMIXED_TVDPLL>;
> + clock-names = "pixel", "engine", "pll";
> + assigned-clocks = <&topckgen CLK_TOP_DPI>;
> + assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
> + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
> + status = "disabled";
> +
> + port {
> + dpi_out: endpoint { };
> + };
> + };
> +
> dsi0: dsi@14013000 {
> compatible = "mediatek,mt8186-dsi";
> reg = <0 0x14013000 0 0x1000>;
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 8/9] dt-bindings: display: mediatek: Fix the fallback for mediatek,mt8186-disp-ccorr
2023-01-11 12:37 [PATCH 0/9] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
` (6 preceding siblings ...)
2023-01-11 12:37 ` [PATCH 7/9] arm64: dts: mediatek: mt8186: Add DPI node Allen-KH Cheng
@ 2023-01-11 12:37 ` Allen-KH Cheng
2023-01-13 19:18 ` Rob Herring
2023-01-11 12:37 ` [PATCH 9/9] arm64: dts: mediatek: mt8186: Add display nodes Allen-KH Cheng
8 siblings, 1 reply; 15+ messages in thread
From: Allen-KH Cheng @ 2023-01-11 12:37 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, hsinyi,
Allen-KH Cheng
The mt8186-disp-ccorr is not fully compatible with the mt8183-disp-ccorr
implementation. It causes a crash when system resumes if it binds to the
device.
We should use mt8192-disp-ccorr as fallback of mt8186-disp-ccorr.
Fixes: 8a26ea19d4dc ("dt-bindings: display: mediatek: add MT8186 SoC binding")
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index 63fb02014a56..117e3db43f84 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -32,7 +32,7 @@ properties:
- items:
- enum:
- mediatek,mt8186-disp-ccorr
- - const: mediatek,mt8183-disp-ccorr
+ - const: mediatek,mt8192-disp-ccorr
reg:
maxItems: 1
--
2.18.0
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 8/9] dt-bindings: display: mediatek: Fix the fallback for mediatek,mt8186-disp-ccorr
2023-01-11 12:37 ` [PATCH 8/9] dt-bindings: display: mediatek: Fix the fallback for mediatek,mt8186-disp-ccorr Allen-KH Cheng
@ 2023-01-13 19:18 ` Rob Herring
0 siblings, 0 replies; 15+ messages in thread
From: Rob Herring @ 2023-01-13 19:18 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Rob Herring, Daniel Vetter, AngeloGioacchino Del Regno,
devicetree, Matthias Brugger, dri-devel, linux-kernel,
Stephen Boyd, linux-arm-kernel, Krzysztof Kozlowski,
linux-mediatek, Project_Global_Chrome_Upstream_Group, hsinyi,
Chun-Kuang Hu, David Airlie, Philipp Zabel
On Wed, 11 Jan 2023 20:37:10 +0800, Allen-KH Cheng wrote:
> The mt8186-disp-ccorr is not fully compatible with the mt8183-disp-ccorr
> implementation. It causes a crash when system resumes if it binds to the
> device.
>
> We should use mt8192-disp-ccorr as fallback of mt8186-disp-ccorr.
>
> Fixes: 8a26ea19d4dc ("dt-bindings: display: mediatek: add MT8186 SoC binding")
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 9/9] arm64: dts: mediatek: mt8186: Add display nodes
2023-01-11 12:37 [PATCH 0/9] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
` (7 preceding siblings ...)
2023-01-11 12:37 ` [PATCH 8/9] dt-bindings: display: mediatek: Fix the fallback for mediatek,mt8186-disp-ccorr Allen-KH Cheng
@ 2023-01-11 12:37 ` Allen-KH Cheng
2023-01-12 10:00 ` Chen-Yu Tsai
8 siblings, 1 reply; 15+ messages in thread
From: Allen-KH Cheng @ 2023-01-11 12:37 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, hsinyi,
Allen-KH Cheng
Add display nodes and GCE info for MT8186 SoC. Also, add GCE
(Global Command Engine) properties to the display nodes in order to
enable the usage of the CMDQ (Command Queue), which is required for
operating the display.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 128 +++++++++++++++++++++++
1 file changed, 128 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index eab30ab01572..8670d37970ef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include <dt-bindings/clock/mt8186-clk.h>
+#include <dt-bindings/gce/mt8186-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8186-memory-port.h>
@@ -632,6 +633,15 @@
clocks = <&clk13m>;
};
+ gce: mailbox@1022c000 {
+ compatible = "mediatek,mt8186-gce";
+ reg = <0 0X1022c000 0 0x4000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+ clock-names = "gce";
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8186-scp";
reg = <0 0x10500000 0 0x40000>,
@@ -1197,6 +1207,20 @@
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
+ };
+
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8186-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+ <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
};
smi_common: smi@14002000 {
@@ -1230,6 +1254,49 @@
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
};
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8186-disp-ovl",
+ "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ ovl0_2l: ovl@14006000 {
+ compatible = "mediatek,mt8186-disp-ovl-2l",
+ "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8186-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8186-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
dpi0: dpi@1400a000 {
compatible = "mediatek,mt8186-dpi";
reg = <0 0x1400a000 0 0x1000>;
@@ -1247,6 +1314,56 @@
};
};
+ ccorr0: ccorr@1400b000 {
+ compatible = "mediatek,mt8186-disp-ccorr",
+ "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400b000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ aal0: aal@1400c000 {
+ compatible = "mediatek,mt8186-disp-aal",
+ "mediatek,mt8183-disp-aal";
+ reg = <0 0x1400c000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ gamma0: gamma@1400d000 {
+ compatible = "mediatek,mt8186-disp-gamma",
+ "mediatek,mt8183-disp-gamma";
+ reg = <0 0x1400d000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ postmask0: postmask@1400e000 {
+ compatible = "mediatek,mt8186-disp-postmask",
+ "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400e000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ dither0: dither@1400f000 {
+ compatible = "mediatek,mt8186-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1400f000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
dsi0: dsi@14013000 {
compatible = "mediatek,mt8186-dsi";
reg = <0 0x14013000 0 0x1000>;
@@ -1280,6 +1397,17 @@
#iommu-cells = <1>;
};
+ rdma1: rdma@1401f000 {
+ compatible = "mediatek,mt8186-disp-rdma",
+ "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1401f000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ };
+
wpesys: clock-controller@14020000 {
compatible = "mediatek,mt8186-wpesys";
reg = <0 0x14020000 0 0x1000>;
--
2.18.0
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 9/9] arm64: dts: mediatek: mt8186: Add display nodes
2023-01-11 12:37 ` [PATCH 9/9] arm64: dts: mediatek: mt8186: Add display nodes Allen-KH Cheng
@ 2023-01-12 10:00 ` Chen-Yu Tsai
0 siblings, 0 replies; 15+ messages in thread
From: Chen-Yu Tsai @ 2023-01-12 10:00 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Stephen Boyd, AngeloGioacchino Del Regno, dri-devel, devicetree,
linux-kernel, Project_Global_Chrome_Upstream_Group,
linux-mediatek, hsinyi, linux-arm-kernel
Hi,
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add display nodes and GCE info for MT8186 SoC. Also, add GCE
> (Global Command Engine) properties to the display nodes in order to
> enable the usage of the CMDQ (Command Queue), which is required for
> operating the display.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 128 +++++++++++++++++++++++
> 1 file changed, 128 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index eab30ab01572..8670d37970ef 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -5,6 +5,7 @@
> */
> /dts-v1/;
> #include <dt-bindings/clock/mt8186-clk.h>
> +#include <dt-bindings/gce/mt8186-gce.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/memory/mt8186-memory-port.h>
> @@ -632,6 +633,15 @@
> clocks = <&clk13m>;
> };
>
> + gce: mailbox@1022c000 {
> + compatible = "mediatek,mt8186-gce";
> + reg = <0 0X1022c000 0 0x4000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
> + #mbox-cells = <2>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
> + clock-names = "gce";
> + };
> +
> scp: scp@10500000 {
> compatible = "mediatek,mt8186-scp";
> reg = <0 0x10500000 0 0x40000>,
> @@ -1197,6 +1207,20 @@
> reg = <0 0x14000000 0 0x1000>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> + };
> +
> + mutex: mutex@14001000 {
> + compatible = "mediatek,mt8186-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> };
>
> smi_common: smi@14002000 {
> @@ -1230,6 +1254,49 @@
> power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> };
>
> + ovl0: ovl@14005000 {
If there's only one instance, you could drop the trailing zero. Same
for all the other nodes.
> + compatible = "mediatek,mt8186-disp-ovl",
> + "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> + };
> +
> + ovl0_2l: ovl@14006000 {
I think this should be "ovl_2l0" or "ovl_2l" instead?
> + compatible = "mediatek,mt8186-disp-ovl-2l",
> + "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + };
Also, this patch is missing the aliases for ovl* and rdma*. Without them
the display driver doesn't properly detect the second pipeline, and only
one CRTC is generated.
ChenYu
^ permalink raw reply [flat|nested] 15+ messages in thread