* [PATCH 0/2] Fix WKUP domain IO PADCONFIG size issue and RPi header support
@ 2023-03-16 10:47 sabiya.d
2023-03-16 10:47 ` [PATCH 1/2] arm64: dts: ti: k3-j784s4-mcu-wakeup: Fix IO PADCONFIG size for wakeup domain sabiya.d
2023-03-16 10:47 ` [PATCH 2/2] arm64: dts: ti: k3-am69-sk: Add pinmux for RPi Header sabiya.d
0 siblings, 2 replies; 4+ messages in thread
From: sabiya.d @ 2023-03-16 10:47 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, linus.walleij
Cc: devicetree, linux-arm-kernel, linux-kernel, sabiya.d, Dasnavis Sabiya
From: Dasnavis Sabiya <sabiya.d@ti.com>
Hi All,
This patch series include the below changes:
1. Fix the incorrect IO PADCONFIG offset size of the wakeup domain for J784S4 SoC
2. Add RPi expansion header support for AM69 SK.
Dasnavis Sabiya (2):
arm64: dts: ti: k3-j784s4-mcu-wakeup: Fix IO PADCONFIG size for wakeup
domain
arm64: dts: ti: k3-am69-sk: Add pinmux for RPi Header
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 72 +++++++++++++++++++
.../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 +-
2 files changed, 73 insertions(+), 1 deletion(-)
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH 1/2] arm64: dts: ti: k3-j784s4-mcu-wakeup: Fix IO PADCONFIG size for wakeup domain 2023-03-16 10:47 [PATCH 0/2] Fix WKUP domain IO PADCONFIG size issue and RPi header support sabiya.d @ 2023-03-16 10:47 ` sabiya.d 2023-03-29 7:49 ` Vaishnav Achath 2023-03-16 10:47 ` [PATCH 2/2] arm64: dts: ti: k3-am69-sk: Add pinmux for RPi Header sabiya.d 1 sibling, 1 reply; 4+ messages in thread From: sabiya.d @ 2023-03-16 10:47 UTC (permalink / raw) To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, linus.walleij Cc: devicetree, linux-arm-kernel, linux-kernel, sabiya.d, Dasnavis Sabiya From: Dasnavis Sabiya <sabiya.d@ti.com> The size of IO PADCONFIG register set of the wakeup domain is incorrect for J784S4. Update the PADCONFIG offset size to the correct value for J784S4 SoC. Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 64bd3dee14aa..c0103513c64c 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -50,7 +50,7 @@ mcu_ram: sram@41c00000 { wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x194>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; -- 2.25.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] arm64: dts: ti: k3-j784s4-mcu-wakeup: Fix IO PADCONFIG size for wakeup domain 2023-03-16 10:47 ` [PATCH 1/2] arm64: dts: ti: k3-j784s4-mcu-wakeup: Fix IO PADCONFIG size for wakeup domain sabiya.d @ 2023-03-29 7:49 ` Vaishnav Achath 0 siblings, 0 replies; 4+ messages in thread From: Vaishnav Achath @ 2023-03-29 7:49 UTC (permalink / raw) To: sabiya.d, nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, linus.walleij Cc: devicetree, linux-arm-kernel, linux-kernel, Dasnavis Sabiya, u-kumar1 Hi Sabiya, On 16/03/23 16:17, sabiya.d@mistralsolutions.com wrote: > From: Dasnavis Sabiya <sabiya.d@ti.com> > > The size of IO PADCONFIG register set of the wakeup domain is incorrect for > J784S4. Update the PADCONFIG offset size to the correct value for > J784S4 SoC. > > Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") > Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi > index 64bd3dee14aa..c0103513c64c 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi > @@ -50,7 +50,7 @@ mcu_ram: sram@41c00000 { > wkup_pmx0: pinctrl@4301c000 { > compatible = "pinctrl-single"; > /* Proxy 0 addressing */ > - reg = <0x00 0x4301c000 0x00 0x178>; > + reg = <0x00 0x4301c000 0x00 0x194>; > #pinctrl-cells = <1>; > pinctrl-single,register-width = <32>; > pinctrl-single,function-mask = <0xffffffff>; Similar feedback as for the J721S2 PADCONFIG patch, see the discussion below, https://lore.kernel.org/all/20230328114742.tnaa5hi3qm3rsgld@ecology/ As suggested by Nishanth, let us do a single fixup to avoid non-addressable regions and fix the padconfig region size. From datasheet I can see that the addresses corresponding to WKUP_PADCONFIG13, WKUP_PADCONFIG25 are missing for J784S4. -- Regards, Vaishnav ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] arm64: dts: ti: k3-am69-sk: Add pinmux for RPi Header 2023-03-16 10:47 [PATCH 0/2] Fix WKUP domain IO PADCONFIG size issue and RPi header support sabiya.d 2023-03-16 10:47 ` [PATCH 1/2] arm64: dts: ti: k3-j784s4-mcu-wakeup: Fix IO PADCONFIG size for wakeup domain sabiya.d @ 2023-03-16 10:47 ` sabiya.d 1 sibling, 0 replies; 4+ messages in thread From: sabiya.d @ 2023-03-16 10:47 UTC (permalink / raw) To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt, linus.walleij Cc: devicetree, linux-arm-kernel, linux-kernel, sabiya.d, Dasnavis Sabiya From: Dasnavis Sabiya <sabiya.d@ti.com> Add pinmux required to bring out the i2c and gpios on 40 pin RPi expansion header on AM69 SK board. Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 72 +++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index bc49ba534790..5d2d96a50921 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -104,6 +104,37 @@ vdd_sd_dv: regulator-tlv71033 { }; }; +&wkup_pmx0 { + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x108, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x10C, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + + mcu_rpi_header_gpio0_pins_default: mcu-rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x190, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ + J784S4_WKUP_IOPAD(0x180, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ + J784S4_WKUP_IOPAD(0x0C4, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ + J784S4_WKUP_IOPAD(0x0C8, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + J784S4_WKUP_IOPAD(0x0C0, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ + J784S4_WKUP_IOPAD(0x120, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ + J784S4_WKUP_IOPAD(0x17C, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ + J784S4_WKUP_IOPAD(0x0FC, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ + J784S4_WKUP_IOPAD(0x0CC, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ + J784S4_WKUP_IOPAD(0x184, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ + >; + }; +}; + &main_pmx0 { main_uart8_pins_default: main-uart8-pins-default { pinctrl-single,pins = < @@ -137,6 +168,25 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ + J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ + J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ + J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ + J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ + J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ + J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ + J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ + J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ + J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ + J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ + J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ + J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ + J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ + >; + }; }; &main_uart8 { @@ -145,6 +195,20 @@ &main_uart8 { pinctrl-0 = <&main_uart8_pins_default>; }; +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -175,6 +239,14 @@ &main_sdhci1 { vqmmc-supply = <&vdd_sd_dv>; }; +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_header_gpio0_pins_default>; +}; + &main_gpio0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; -- 2.25.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-03-29 7:50 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-03-16 10:47 [PATCH 0/2] Fix WKUP domain IO PADCONFIG size issue and RPi header support sabiya.d 2023-03-16 10:47 ` [PATCH 1/2] arm64: dts: ti: k3-j784s4-mcu-wakeup: Fix IO PADCONFIG size for wakeup domain sabiya.d 2023-03-29 7:49 ` Vaishnav Achath 2023-03-16 10:47 ` [PATCH 2/2] arm64: dts: ti: k3-am69-sk: Add pinmux for RPi Header sabiya.d
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