From: Drew Fustini <dfustini@baylibre.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Ved Shanbhogue" <ved@rivosinc.com>,
"Kornel Dulęba" <mindal@semihalf.com>,
"Adrien Ricciardi" <aricciardi@baylibre.com>,
"Nicolas Pitre" <npitre@baylibre.com>,
"Fenghua Yu" <fenghua.yu@intel.com>,
"Reinette Chatre" <reinette.chatre@intel.com>,
"Babu Moger" <babu.moger@amd.com>,
"Peter Newman" <peternewman@google.com>,
x86@kernel.org, "Rob Herring" <robh+dt@kernel.org>,
"James Morse" <james.morse@arm.com>
Cc: Drew Fustini <dfustini@baylibre.com>
Subject: [RFC PATCH 19/21] DO_NOT_MERGE riscv: dts: qemu: add dump from riscv-cbqri-rfc
Date: Wed, 19 Apr 2023 04:11:09 -0700 [thread overview]
Message-ID: <20230419111111.477118-20-dfustini@baylibre.com> (raw)
In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com>
Dumped dtb from qemu branch riscv-cbqri-rfc which is on top of qemu
master (tag: v8.0.0-rc4) with qemu/VERSION of 7.2.94 invoked with:
qemu-system-riscv64 \
-M virt \
-nographic \
-smp 8 \
-bios output/images/fw_jump.elf \
-kernel $HOME/kernel/cbqri-linux/arch/riscv/boot/Image \
-append "root=/dev/vda ro" \
-drive file=output/images/rootfs.ext2,format=raw,id=hd0 \
-device virtio-blk-device,drive=hd0 \
-machine dumpdtb=qemu.dtb
Link: https://gitlab.baylibre.com/baylibre/qemu/-/tree/riscv-cbqri-rfc
Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com>
Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
---
Note: this is necessary as Qemu branch riscv-cbqri-rfc does not yet
support generating a dtb with the nodes and properties needed for CBQRI
controllers. Thus, those lines must be added in the next patch and an
external dtb (qemu-virt-cbqri.dtb) built by Linux is used when
invoking qemu-system-riscv64
arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts | 371 +++++++++++++++++++
1 file changed, 371 insertions(+)
create mode 100644 arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts
diff --git a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts
new file mode 100644
index 000000000000..400ed48a06af
--- /dev/null
+++ b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "riscv-virtio";
+ model = "riscv-virtio,qemu";
+
+ fw-cfg@10100000 {
+ dma-coherent;
+ reg = <0x00 0x10100000 0x00 0x18>;
+ compatible = "qemu,fw-cfg-mmio";
+ };
+
+ flash@20000000 {
+ bank-width = <0x04>;
+ reg = <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>;
+ compatible = "cfi-flash";
+ };
+
+ chosen {
+ bootargs = "root=/dev/vda ro ftrace=function_graph ftrace_filter=\"*resctrl*,*qos*\"";
+ rng-seed = <0xb87c09c5 0xc8f0c713 0x9c217b2a 0xa6f44e14 0xb6e99df6 0x205d482b 0x6d4c34f4 0x6466fc08>;
+ stdout-path = "/soc/serial@10000000";
+ };
+
+ poweroff {
+ value = <0x5555>;
+ offset = <0x00>;
+ regmap = <0x12>;
+ compatible = "syscon-poweroff";
+ };
+
+ reboot {
+ value = <0x7777>;
+ offset = <0x00>;
+ regmap = <0x12>;
+ compatible = "syscon-reboot";
+ };
+
+ platform-bus@4000000 {
+ interrupt-parent = <0x11>;
+ ranges = <0x00 0x00 0x4000000 0x2000000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "qemu,platform\0simple-bus";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x00 0x8000000>;
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0x989680>;
+
+ cpu@0 {
+ phandle = <0x0f>;
+ device_type = "cpu";
+ reg = <0x00>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa = "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x10>;
+ };
+ };
+
+ cpu@1 {
+ phandle = <0x0d>;
+ device_type = "cpu";
+ reg = <0x01>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa = "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x0e>;
+ };
+ };
+
+ cpu@2 {
+ phandle = <0x0b>;
+ device_type = "cpu";
+ reg = <0x02>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa = "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x0c>;
+ };
+ };
+
+ cpu@3 {
+ phandle = <0x09>;
+ device_type = "cpu";
+ reg = <0x03>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa = "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x0a>;
+ };
+ };
+
+ cpu@4 {
+ phandle = <0x07>;
+ device_type = "cpu";
+ reg = <0x04>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa = "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x08>;
+ };
+ };
+
+ cpu@5 {
+ phandle = <0x05>;
+ device_type = "cpu";
+ reg = <0x05>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa = "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x06>;
+ };
+ };
+
+ cpu@6 {
+ phandle = <0x03>;
+ device_type = "cpu";
+ reg = <0x06>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa = "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x04>;
+ };
+ };
+
+ cpu@7 {
+ phandle = <0x01>;
+ device_type = "cpu";
+ reg = <0x07>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,cboz-block-size = <0x40>;
+ riscv,cbom-block-size = <0x40>;
+ riscv,isa = "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu";
+ mmu-type = "riscv,sv57";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x02>;
+ };
+ };
+
+ cpu-map {
+
+ cluster0 {
+
+ core0 {
+ cpu = <0x0f>;
+ };
+
+ core1 {
+ cpu = <0x0d>;
+ };
+
+ core2 {
+ cpu = <0x0b>;
+ };
+
+ core3 {
+ cpu = <0x09>;
+ };
+
+ core4 {
+ cpu = <0x07>;
+ };
+
+ core5 {
+ cpu = <0x05>;
+ };
+
+ core6 {
+ cpu = <0x03>;
+ };
+
+ core7 {
+ cpu = <0x01>;
+ };
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "simple-bus";
+ ranges;
+
+ pmu {
+ riscv,event-to-mhpmcounters = <0x01 0x01 0x7fff9 0x02 0x02 0x7fffc 0x10019 0x10019 0x7fff8 0x1001b 0x1001b 0x7fff8 0x10021 0x10021 0x7fff8 0x00 0x00 0x00 0x00 0x00>;
+ compatible = "riscv,pmu";
+ };
+
+ rtc@101000 {
+ interrupts = <0x0b>;
+ interrupt-parent = <0x11>;
+ reg = <0x00 0x101000 0x00 0x1000>;
+ compatible = "google,goldfish-rtc";
+ };
+
+ serial@10000000 {
+ interrupts = <0x0a>;
+ interrupt-parent = <0x11>;
+ clock-frequency = "\08@";
+ reg = <0x00 0x10000000 0x00 0x100>;
+ compatible = "ns16550a";
+ };
+
+ test@100000 {
+ phandle = <0x12>;
+ reg = <0x00 0x100000 0x00 0x1000>;
+ compatible = "sifive,test1\0sifive,test0\0syscon";
+ };
+
+ pci@30000000 {
+ interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x11 0x20 0x00 0x00 0x00 0x02 0x11 0x21 0x00 0x00 0x00 0x03 0x11 0x22 0x00 0x00 0x00 0x04 0x11 0x23 0x800 0x00 0x00 0x01 0x11 0x21 0x800 0x00 0x00 0x02 0x11 0x22 0x800 0x00 0x00 0x03 0x11 0x23 0x800 0x00 0x00 0x04 0x11 0x20 0x1000 0x00 0x00 0x01 0x11 0x22 0x1000 0x00 0x00 0x02 0x11 0x23 0x1000 0x00 0x00 0x03 0x11 0x20 0x1000 0x00 0x00 0x04 0x11 0x21 0x1800 0x00 0x00 0x01 0x11 0x23 0x1800 0x00 0x00 0x02 0x11 0x20 0x1800 0x00 0x00 0x03 0x11 0x21 0x1800 0x00 0x00 0x04 0x11 0x22>;
+ ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>;
+ reg = <0x00 0x30000000 0x00 0x10000000>;
+ dma-coherent;
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <0x00>;
+ device_type = "pci";
+ compatible = "pci-host-ecam-generic";
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ #address-cells = <0x03>;
+ };
+
+ virtio_mmio@10008000 {
+ interrupts = <0x08>;
+ interrupt-parent = <0x11>;
+ reg = <0x00 0x10008000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10007000 {
+ interrupts = <0x07>;
+ interrupt-parent = <0x11>;
+ reg = <0x00 0x10007000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10006000 {
+ interrupts = <0x06>;
+ interrupt-parent = <0x11>;
+ reg = <0x00 0x10006000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10005000 {
+ interrupts = <0x05>;
+ interrupt-parent = <0x11>;
+ reg = <0x00 0x10005000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10004000 {
+ interrupts = <0x04>;
+ interrupt-parent = <0x11>;
+ reg = <0x00 0x10004000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10003000 {
+ interrupts = <0x03>;
+ interrupt-parent = <0x11>;
+ reg = <0x00 0x10003000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10002000 {
+ interrupts = <0x02>;
+ interrupt-parent = <0x11>;
+ reg = <0x00 0x10002000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10001000 {
+ interrupts = <0x01>;
+ interrupt-parent = <0x11>;
+ reg = <0x00 0x10001000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ plic@c000000 {
+ phandle = <0x11>;
+ riscv,ndev = <0x5f>;
+ reg = <0x00 0xc000000 0x00 0x600000>;
+ interrupts-extended = <0x10 0x0b 0x10 0x09 0x0e 0x0b 0x0e 0x09 0x0c 0x0b 0x0c 0x09 0x0a 0x0b 0x0a 0x09 0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>;
+ interrupt-controller;
+ compatible = "sifive,plic-1.0.0\0riscv,plic0";
+ #address-cells = <0x00>;
+ #interrupt-cells = <0x01>;
+ };
+
+ clint@2000000 {
+ interrupts-extended = <0x10 0x03 0x10 0x07 0x0e 0x03 0x0e 0x07 0x0c 0x03 0x0c 0x07 0x0a 0x03 0x0a 0x07 0x08 0x03 0x08 0x07 0x06 0x03 0x06 0x07 0x04 0x03 0x04 0x07 0x02 0x03 0x02 0x07>;
+ reg = <0x00 0x2000000 0x00 0x10000>;
+ compatible = "sifive,clint0\0riscv,clint0";
+ };
+ };
+};
--
2.34.1
next prev parent reply other threads:[~2023-04-19 11:12 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 11:10 [RFC PATCH 00/21] RISC-V: QoS: add CBQRI resctrl interface Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 01/21] RISC-V: Detect the Ssqosid extension Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 02/21] RISC-V: Add support for sqoscfg CSR Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 03/21] RISC-V: QoS: define properties of CBQRI controllers Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 04/21] RISC-V: QoS: define CBQRI capacity and bandwidth capabilities Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 05/21] RISC-V: QoS: define prototypes for resctrl interface Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 06/21] RISC-V: QoS: define CBQRI resctrl resources and domains Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 07/21] RISC-V: QoS: add resctrl interface for CBQRI controllers Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 08/21] RISC-V: QoS: expose implementation to resctrl Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 09/21] RISC-V: QoS: add late_initcall to setup resctrl interface Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 10/21] RISC-V: QoS: make CONFIG_RISCV_ISA_SSQOSID select resctrl Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 11/21] RISC-V: QoS: add to build when CONFIG_RISCV_ISA_SSQOSID set Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 12/21] dt-bindings: riscv: add riscv,cbqri bindings Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 13/21] DO_NOT_MERGE dt-bindings: add foobar vendor-prefix Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 14/21] DO_NOT_MERGE dt-bindings: soc: add Foobar SoC cache controller Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 15/21] DO_NOT_MERGE dt-bindings: soc: add Foobar SoC memory controller Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 16/21] DO_NOT_MERGE soc: add Foobar SoC cache controller driver Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 17/21] DO_NOT_MERGE soc: add Foobar SoC memory " Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 18/21] DO_NOT_MERGE soc: build Foobar SoC drivers Drew Fustini
2023-04-19 11:11 ` Drew Fustini [this message]
2023-04-19 11:11 ` [RFC PATCH 20/21] DO_NOT_MERGE riscv: dts: qemu: add cbqri-capable controllers Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 21/21] DO_NOT_MERGE riscv: dts: build qemu virt device tree Drew Fustini
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