From: Drew Fustini <dfustini@baylibre.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Ved Shanbhogue" <ved@rivosinc.com>,
"Kornel Dulęba" <mindal@semihalf.com>,
"Adrien Ricciardi" <aricciardi@baylibre.com>,
"Nicolas Pitre" <npitre@baylibre.com>,
"Fenghua Yu" <fenghua.yu@intel.com>,
"Reinette Chatre" <reinette.chatre@intel.com>,
"Babu Moger" <babu.moger@amd.com>,
"Peter Newman" <peternewman@google.com>,
x86@kernel.org, "Rob Herring" <robh+dt@kernel.org>,
"James Morse" <james.morse@arm.com>
Cc: Drew Fustini <dfustini@baylibre.com>
Subject: [RFC PATCH 05/21] RISC-V: QoS: define prototypes for resctrl interface
Date: Wed, 19 Apr 2023 04:10:55 -0700 [thread overview]
Message-ID: <20230419111111.477118-6-dfustini@baylibre.com> (raw)
In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com>
Define the prototypes for the resctrl interface functions that are
implemented on RISC-V.
Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com>
Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
---
include/linux/riscv_qos.h | 58 +++++++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/include/linux/riscv_qos.h b/include/linux/riscv_qos.h
index 95016810b575..537e503a8e99 100644
--- a/include/linux/riscv_qos.h
+++ b/include/linux/riscv_qos.h
@@ -3,6 +3,7 @@
#ifndef __LINUX_RISCV_QOS_H
#define __LINUX_RISCV_QOS_H
+#include <linux/resctrl_types.h>
#include <linux/iommu.h>
#include <linux/types.h>
@@ -31,4 +32,61 @@ struct cbqri_controller_info {
extern struct list_head cbqri_controllers;
+bool resctrl_arch_alloc_capable(void);
+bool resctrl_arch_mon_capable(void);
+bool resctrl_arch_is_llc_occupancy_enabled(void);
+bool resctrl_arch_is_mbm_local_enabled(void);
+bool resctrl_arch_is_mbm_total_enabled(void);
+
+struct rdt_resource;
+/*
+ * Note about terminology between x86 (Intel RDT/AMD QoS) and RISC-V:
+ * CLOSID on x86 is RCID on RISC-V
+ * RMID on x86 is MCID on RISC-V
+ * CDP on x86 is AT (access type) on RISC-V
+ */
+bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level ignored);
+bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid);
+bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid);
+int resctrl_arch_mon_ctx_alloc_no_wait(struct rdt_resource *r, int evtid);
+void resctrl_arch_mon_ctx_free(struct rdt_resource *r, int evtid, int ctx);
+void resctrl_arch_reset_resources(void);
+void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid);
+u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid);
+int resctrl_arch_set_cdp_enabled(enum resctrl_res_level ignored, bool enable);
+void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32 rmid);
+void resctrl_arch_set_cpu_default_closid(int cpu, u32 closid);
+void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 pmg);
+u32 resctrl_arch_system_num_rmid_idx(void);
+void resctrl_sched_in(void);
+
+static inline bool resctrl_arch_event_is_free_running(enum resctrl_event_id evt)
+{
+ /* must be true for resctrl L3 monitoring files to be created */
+ return true;
+}
+
+static inline unsigned int resctrl_arch_round_mon_val(unsigned int val)
+{
+ return val;
+}
+
+/* Pseudo lock is not supported on RISC-V */
+static inline int resctrl_arch_pseudo_lock_fn(void *_plr) { return 0; }
+static inline int resctrl_arch_measure_l2_residency(void *_plr) { return 0; }
+static inline int resctrl_arch_measure_l3_residency(void *_plr) { return 0; }
+static inline int resctrl_arch_measure_cycles_lat_fn(void *_plr) { return 0; }
+static inline u64 resctrl_arch_get_prefetch_disable_bits(void) { return 0; }
+
+/* Not needed for RISC-V */
+bool resctrl_arch_match_iommu_closid(struct iommu_group *group, u32 closid);
+bool resctrl_arch_match_iommu_closid_rmid(struct iommu_group *group, u32 closid, u32 rmid);
+int resctrl_arch_set_iommu_closid_rmid(struct iommu_group *group, u32 closid, u32 rmid);
+
+/* Not needed for RISC-V */
+static inline void resctrl_arch_enable_mon(void) { }
+static inline void resctrl_arch_disable_mon(void) { }
+static inline void resctrl_arch_enable_alloc(void) { }
+static inline void resctrl_arch_disable_alloc(void) { }
+
#endif /* __LINUX_RISCV_QOS_H */
--
2.34.1
next prev parent reply other threads:[~2023-04-19 11:11 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 11:10 [RFC PATCH 00/21] RISC-V: QoS: add CBQRI " Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 01/21] RISC-V: Detect the Ssqosid extension Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 02/21] RISC-V: Add support for sqoscfg CSR Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 03/21] RISC-V: QoS: define properties of CBQRI controllers Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 04/21] RISC-V: QoS: define CBQRI capacity and bandwidth capabilities Drew Fustini
2023-04-19 11:10 ` Drew Fustini [this message]
2023-04-19 11:10 ` [RFC PATCH 06/21] RISC-V: QoS: define CBQRI resctrl resources and domains Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 07/21] RISC-V: QoS: add resctrl interface for CBQRI controllers Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 08/21] RISC-V: QoS: expose implementation to resctrl Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 09/21] RISC-V: QoS: add late_initcall to setup resctrl interface Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 10/21] RISC-V: QoS: make CONFIG_RISCV_ISA_SSQOSID select resctrl Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 11/21] RISC-V: QoS: add to build when CONFIG_RISCV_ISA_SSQOSID set Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 12/21] dt-bindings: riscv: add riscv,cbqri bindings Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 13/21] DO_NOT_MERGE dt-bindings: add foobar vendor-prefix Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 14/21] DO_NOT_MERGE dt-bindings: soc: add Foobar SoC cache controller Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 15/21] DO_NOT_MERGE dt-bindings: soc: add Foobar SoC memory controller Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 16/21] DO_NOT_MERGE soc: add Foobar SoC cache controller driver Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 17/21] DO_NOT_MERGE soc: add Foobar SoC memory " Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 18/21] DO_NOT_MERGE soc: build Foobar SoC drivers Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 19/21] DO_NOT_MERGE riscv: dts: qemu: add dump from riscv-cbqri-rfc Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 20/21] DO_NOT_MERGE riscv: dts: qemu: add cbqri-capable controllers Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 21/21] DO_NOT_MERGE riscv: dts: build qemu virt device tree Drew Fustini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230419111111.477118-6-dfustini@baylibre.com \
--to=dfustini@baylibre.com \
--cc=aricciardi@baylibre.com \
--cc=babu.moger@amd.com \
--cc=conor.dooley@microchip.com \
--cc=fenghua.yu@intel.com \
--cc=james.morse@arm.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mindal@semihalf.com \
--cc=npitre@baylibre.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=peternewman@google.com \
--cc=reinette.chatre@intel.com \
--cc=robh+dt@kernel.org \
--cc=ved@rivosinc.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome