From: Sean Nyekjaer <sean@geanix.com>
To: Lee Jones <lee@kernel.org>
Cc: p.paillet@st.com, Sean Nyekjaer <sean@geanix.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH 1/2] mfd: stpmic1: fixup main control register and bits naming
Date: Fri, 28 Apr 2023 13:28:45 +0200 [thread overview]
Message-ID: <20230428112847.2146348-1-sean@geanix.com> (raw)
Fixup main control register and bits naming so the match the naming from
the datasheet.
https://www.st.com/resource/en/datasheet/stpmic1.pdf
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
---
drivers/mfd/stpmic1.c | 4 ++--
include/linux/mfd/stpmic1.h | 12 ++++++------
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c
index 8db1530d9bac..4c9b18d9dec8 100644
--- a/drivers/mfd/stpmic1.c
+++ b/drivers/mfd/stpmic1.c
@@ -19,7 +19,7 @@
static const struct regmap_range stpmic1_readable_ranges[] = {
regmap_reg_range(TURN_ON_SR, VERSION_SR),
- regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
+ regmap_reg_range(MAIN_CR, LDO6_STDBY_CR),
regmap_reg_range(BST_SW_CR, BST_SW_CR),
regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
@@ -30,7 +30,7 @@ static const struct regmap_range stpmic1_readable_ranges[] = {
};
static const struct regmap_range stpmic1_writeable_ranges[] = {
- regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
+ regmap_reg_range(MAIN_CR, LDO6_STDBY_CR),
regmap_reg_range(BST_SW_CR, BST_SW_CR),
regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
diff --git a/include/linux/mfd/stpmic1.h b/include/linux/mfd/stpmic1.h
index fa3f99f7e9a1..dc00bac24f5a 100644
--- a/include/linux/mfd/stpmic1.h
+++ b/include/linux/mfd/stpmic1.h
@@ -15,7 +15,7 @@
#define RREQ_STATE_SR 0x5
#define VERSION_SR 0x6
-#define SWOFF_PWRCTRL_CR 0x10
+#define MAIN_CR 0x10
#define PADS_PULL_CR 0x11
#define BUCKS_PD_CR 0x12
#define LDO14_PD_CR 0x13
@@ -148,14 +148,14 @@
#define LDO_BYPASS_MASK BIT(7)
/* Main PMIC Control Register
- * SWOFF_PWRCTRL_CR
+ * MAIN_CR
* Address : 0x10
*/
-#define ICC_EVENT_ENABLED BIT(4)
+#define OCP_OFF_DBG BIT(4)
#define PWRCTRL_POLARITY_HIGH BIT(3)
-#define PWRCTRL_PIN_VALID BIT(2)
-#define RESTART_REQUEST_ENABLED BIT(1)
-#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
+#define PWRCTRL_ENABLE BIT(2)
+#define RESTART_REQUEST_ENABLE BIT(1)
+#define SOFTWARE_SWITCH_OFF BIT(0)
/* Main PMIC PADS Control Register
* PADS_PULL_CR
--
2.40.0
next reply other threads:[~2023-04-28 11:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 11:28 Sean Nyekjaer [this message]
2023-04-28 11:28 ` [PATCH 2/2] mfd: stpmic1: add pmic poweroff via sys-off handler Sean Nyekjaer
2023-05-02 6:17 ` Sean Nyekjær
2023-05-15 12:46 ` Lee Jones
2023-05-15 12:43 ` [PATCH 1/2] mfd: stpmic1: fixup main control register and bits naming Lee Jones
2023-05-16 6:52 ` Sean Nyekjær
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