* [PATCH 1/4] arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node
2023-05-05 14:14 [PATCH 0/4] arm64: dts: ti: j721e: Add HyperFlash support Vaishnav Achath
@ 2023-05-05 14:14 ` Vaishnav Achath
2023-05-05 14:14 ` [PATCH 2/4] arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node Vaishnav Achath
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Vaishnav Achath @ 2023-05-05 14:14 UTC (permalink / raw)
To: nm, afd, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: devicetree, linux-arm-kernel, linux-kernel, u-kumar1, vaishnav.a
J721E has a Flash SubSystem that has one OSPI and one HyperBus with
muxed datapath and another independent OSPI. Add DT nodes for HyperBus
controller and keep it disabled and model the data path selection mux as a
reg-mux. Also the register region range for FSS only have description
for registers up to 0x7c, update that and fix the fss node name to fix
DT compile warning.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 25 +++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 24e8125db8c4..6dfd76619a4a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -174,13 +174,34 @@
status = "disabled";
};
- fss: fss@47000000 {
+ fss: bus@47000000 {
compatible = "simple-bus";
- reg = <0x0 0x47000000 0x0 0x100>;
+ reg = <0x0 0x47000000 0x0 0x7c>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ hbmc_mux: mux-controller@47000004 {
+ compatible = "reg-mux";
+ reg = <0x00 0x47000004 0x00 0x2>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4 0x2>; /* HBMC select */
+ };
+
+ hbmc: hyperbus@47034000 {
+ compatible = "ti,am654-hbmc";
+ reg = <0x00 0x47034000 0x00 0x0c>,
+ <0x05 0x00000000 0x01 0x0000000>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 0>;
+ assigned-clocks = <&k3_clks 102 5>;
+ assigned-clock-rates = <333333333>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ mux-controls = <&hbmc_mux 0>;
+ status = "disabled";
+ };
+
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/4] arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node
2023-05-05 14:14 [PATCH 0/4] arm64: dts: ti: j721e: Add HyperFlash support Vaishnav Achath
2023-05-05 14:14 ` [PATCH 1/4] arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node Vaishnav Achath
@ 2023-05-05 14:14 ` Vaishnav Achath
2023-05-05 14:14 ` [PATCH 3/4] arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux Vaishnav Achath
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Vaishnav Achath @ 2023-05-05 14:14 UTC (permalink / raw)
To: nm, afd, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: devicetree, linux-arm-kernel, linux-kernel, u-kumar1, vaishnav.a
J721E SoM has a HyperFlash and Hyperram connected to HyperBus memory
controller. HyperBus is muxed with OSPI and only one controller can be
active at a time, therefore keep HyperBus node disabled. Bootloader will
detect the external mux state through a wkup gpio and enable the node as
required.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 35 +++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index e289d5b44356..d7cc40486e42 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -165,6 +165,25 @@
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
>;
};
+
+ mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */
+ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */
+ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */
+ J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */
+ J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */
+ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */
+ J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */
+ J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */
+ J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */
+ J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */
+ J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */
+ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */
+ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */
+ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */
+ >;
+ };
};
&ospi0 {
@@ -185,6 +204,22 @@
};
};
+&hbmc {
+ /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
+ * appropriate node based on board detection
+ */
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+ ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
+ <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
+
+ flash@0,0 {
+ compatible = "cypress,hyperflash", "cfi-flash";
+ reg = <0x00 0x00 0x4000000>;
+ };
+};
+
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 3/4] arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux
2023-05-05 14:14 [PATCH 0/4] arm64: dts: ti: j721e: Add HyperFlash support Vaishnav Achath
2023-05-05 14:14 ` [PATCH 1/4] arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node Vaishnav Achath
2023-05-05 14:14 ` [PATCH 2/4] arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node Vaishnav Achath
@ 2023-05-05 14:14 ` Vaishnav Achath
2023-05-05 14:14 ` [PATCH 4/4] arm64: dts: ti: k3-j721e-common-proc-board: " Vaishnav Achath
2023-05-13 12:35 ` [PATCH 0/4] arm64: dts: ti: j721e: Add HyperFlash support Vaishnav Achath
4 siblings, 0 replies; 6+ messages in thread
From: Vaishnav Achath @ 2023-05-05 14:14 UTC (permalink / raw)
To: nm, afd, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: devicetree, linux-arm-kernel, linux-kernel, u-kumar1, vaishnav.a
J7200 common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 63633e4f6c59..f5cbb4b7a9fb 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -98,6 +98,12 @@
>;
};
+ wkup_gpio_pins_default: wkup-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
+ >;
+ };
+
mcu_mdio_pins_default: mcu-mdio1-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
@@ -187,6 +193,11 @@
status = "disabled";
};
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
&wkup_gpio1 {
status = "disabled";
};
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 4/4] arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select pinmux
2023-05-05 14:14 [PATCH 0/4] arm64: dts: ti: j721e: Add HyperFlash support Vaishnav Achath
` (2 preceding siblings ...)
2023-05-05 14:14 ` [PATCH 3/4] arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux Vaishnav Achath
@ 2023-05-05 14:14 ` Vaishnav Achath
2023-05-13 12:35 ` [PATCH 0/4] arm64: dts: ti: j721e: Add HyperFlash support Vaishnav Achath
4 siblings, 0 replies; 6+ messages in thread
From: Vaishnav Achath @ 2023-05-05 14:14 UTC (permalink / raw)
To: nm, afd, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: devicetree, linux-arm-kernel, linux-kernel, u-kumar1, vaishnav.a
J721E common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 7db0603125aa..b7a2f23b2c67 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -363,6 +363,12 @@
J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
>;
};
+
+ wkup_gpio_pins_default: wkup-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
+ >;
+ };
};
&wkup_uart0 {
@@ -420,6 +426,11 @@
status = "disabled";
};
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
&wkup_gpio1 {
status = "disabled";
};
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 0/4] arm64: dts: ti: j721e: Add HyperFlash support
2023-05-05 14:14 [PATCH 0/4] arm64: dts: ti: j721e: Add HyperFlash support Vaishnav Achath
` (3 preceding siblings ...)
2023-05-05 14:14 ` [PATCH 4/4] arm64: dts: ti: k3-j721e-common-proc-board: " Vaishnav Achath
@ 2023-05-13 12:35 ` Vaishnav Achath
4 siblings, 0 replies; 6+ messages in thread
From: Vaishnav Achath @ 2023-05-13 12:35 UTC (permalink / raw)
To: nm, afd, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: devicetree, linux-arm-kernel, linux-kernel, u-kumar1
Hi,
On 05/05/23 19:44, Vaishnav Achath wrote:
> This series adds hyperflash support for J721E. J721E SoC has HyperBus
> and OSPI controller muxed within the FSS subsystem and the J721E SoM
> has a 64 MiB S28 OSPI flash and a 64 MiB Hyperflash present which is
> muxed externally also.
I have sent a v2 of this series with feedback addressed from a similar
series and also adding the hyperflash partitions:
https://lore.kernel.org/all/20230513123313.11462-1-vaishnav.a@ti.com/
Thanks and Regards,
Vaishnav
>
> * Patch 1/4 adds the hyperbus controller nodes and fixes DT compile
> warnings.
> * Patch 2/4 adds the hyperflash support in the SoM DTS.
> * Patch 3 and 4/4 enables the pinmux for external mux that selects
> between hyperflash or OSPI NOR flash, this is done for J7200 and
> J721E platforms since it is required in U-Boot and helps keep the
> DT in sync.
>
> Patch 1/4 depends on the following patch:
> https://lore.kernel.org/all/20230424184810.29453-1-afd@ti.com/
>
> Patch 3 depends on the below fix for pinmux offsets in J7200:
> https://lore.kernel.org/all/20230419040007.3022780-2-u-kumar1@ti.com/
>
> Bootlog and basic hyperflash erase-write-read test:
> https://gist.github.com/vaishnavachath/be652108f3e360f1e2d41b499df844ef
>
> Thanks and Regards,
> Vaishnav
>
> Vaishnav Achath (4):
> arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node
> arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node
> arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select
> pinmux
> arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select
> pinmux
>
> .../dts/ti/k3-j7200-common-proc-board.dts | 11 ++++++
> .../dts/ti/k3-j721e-common-proc-board.dts | 11 ++++++
> .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 25 +++++++++++--
> arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 35 +++++++++++++++++++
> 4 files changed, 80 insertions(+), 2 deletions(-)
>
^ permalink raw reply [flat|nested] 6+ messages in thread