[PATCH v2 0/4] arm64: dts: ti: j721e: Add HyperFlash support

[PATCH v2 0/4] arm64: dts: ti: j721e: Add HyperFlash support

[Vaishnav Achath]

This series adds hyperflash support for J721E. J721E SoC has HyperBus
and OSPI controller muxed within the FSS subsystem and the J721E SoM
has a 64 MiB S28 OSPI flash and a 64 MiB Hyperflash present which is
muxed externally also.

Changelog:
V1->V2:
 * Address feedback in similar series:
 https://lore.kernel.org/all/feddcd03-1848-b667-6a38-ae7c0f6ff160@ti.com/
 * Add partitions information in Hyperflash node.

V1: https://lore.kernel.org/all/20230505141407.15134-1-vaishnav.a@ti.com/

* Patch 1/4 adds the hyperbus controller nodes and fixes DT compile
warnings.
* Patch 2/4 adds the hyperflash support in the SoM DTS.
* Patch 3 and 4/4 enables the pinmux for external mux that selects
between hyperflash or OSPI NOR flash, this is done for J7200 and 
J721E platforms since it is required in U-Boot and helps keep the
DT in sync.

Patch 1/4 depends on the following patch:
https://lore.kernel.org/all/20230424184810.29453-1-afd@ti.com/

Patch 3 depends on the below fix for pinmux offsets in J7200:
https://lore.kernel.org/all/20230419040007.3022780-2-u-kumar1@ti.com/

Bootlog and basic hyperflash erase-write-read test:
https://gist.github.com/vaishnavachath/be652108f3e360f1e2d41b499df844ef

Thanks and Regards,
Vaishnav

Vaishnav Achath (4):
  arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node
  arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node
  arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select
    pinmux
  arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select
    pinmux

 .../dts/ti/k3-j7200-common-proc-board.dts     | 11 +++
 .../dts/ti/k3-j721e-common-proc-board.dts     | 11 +++
 .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      | 21 ++++++
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi   | 71 +++++++++++++++++++
 4 files changed, 114 insertions(+)

-- 
2.17.1

[PATCH v2 1/4] arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node

[Vaishnav Achath]

J721E has a Flash SubSystem that has one OSPI and one HyperBus with
muxed datapath and another independent OSPI. Add DT nodes for HyperBus
controller and keep it disabled and model the data path selection mux as a
reg-mux.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---

V1->V2:
 * Drop register region size update as the memory maps mentions
 256 Bytes for these regions.
 * Drop FSS node rename as the fix is already present in next.

Depends on :
https://lore.kernel.org/all/20230424184810.29453-1-afd@ti.com/

 .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 6237e1f3a477..526886e0c4f4 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -181,6 +181,27 @@
 		#size-cells = <2>;
 		ranges;
 
+		hbmc_mux: mux-controller@47000004 {
+			compatible = "reg-mux";
+			reg = <0x00 0x47000004 0x00 0x2>;
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x4 0x2>; /* HBMC select */
+		};
+
+		hbmc: hyperbus@47034000 {
+			compatible = "ti,am654-hbmc";
+			reg = <0x00 0x47034000 0x00 0x100>,
+				<0x05 0x00000000 0x01 0x0000000>;
+			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+			clocks = <&k3_clks 102 0>;
+			assigned-clocks = <&k3_clks 102 5>;
+			assigned-clock-rates = <333333333>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			mux-controls = <&hbmc_mux 0>;
+			status = "disabled";
+		};
+
 		ospi0: spi@47040000 {
 			compatible = "ti,am654-ospi", "cdns,qspi-nor";
 			reg = <0x0 0x47040000 0x0 0x100>,
-- 
2.17.1

[PATCH v2 2/4] arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node

[Vaishnav Achath]

J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory
controller, add corresponding node, pinmux and partitions for the same.
HyperBus is muxed with OSPI and only one controller can be active at a
time, therefore keep HyperBus node disabled. Bootloader will detect the
external mux state through a wkup gpio and enable the node as required.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---

V1->V2:
 * Add partition information.

 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 71 +++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index e289d5b44356..b96e5fdddb4b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -165,6 +165,25 @@
 			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
 		>;
 	};
+
+	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CK */
+			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CKn */
+			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */
+			J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */
+			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */
+			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1)   /* MCU_HYPERBUS0_RWDS */
+			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1)   /* MCU_HYPERBUS0_DQ0 */
+			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ1 */
+			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ2 */
+			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ3 */
+			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ4 */
+			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ5 */
+			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ6 */
+			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ7 */
+		>;
+	};
 };
 
 &ospi0 {
@@ -185,6 +204,58 @@
 	};
 };
 
+&hbmc {
+	/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
+	 * appropriate node based on board detection
+	 */
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
+		 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
+
+	flash@0,0 {
+		compatible = "cypress,hyperflash", "cfi-flash";
+		reg = <0x00 0x00 0x4000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "hbmc.tiboot3";
+				reg = <0x0 0x80000>;
+			};
+
+			partition@80000 {
+				label = "hbmc.tispl";
+				reg = <0x80000 0x200000>;
+			};
+
+			partition@280000 {
+				label = "hbmc.u-boot";
+				reg = <0x280000 0x400000>;
+			};
+
+			partition@680000 {
+				label = "hbmc.env";
+				reg = <0x680000 0x40000>;
+			};
+
+			partition@6c0000 {
+				label = "hbmc.sysfw";
+				reg = <0x6c0000 0x100000>;
+			};
+
+			partition@800000 {
+				label = "hbmc.rootfs";
+				reg = <0x800000 0x3800000>;
+			};
+		};
+	};
+};
+
 &mailbox0_cluster0 {
 	status = "okay";
 	interrupts = <436>;
-- 
2.17.1

[PATCH v2 3/4] arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux

[Vaishnav Achath]

J7200 common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 0cc0e1dc40c5..e1017027d649 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -97,6 +97,12 @@
 		>;
 	};
 
+	wkup_gpio_pins_default: wkup-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
+		>;
+	};
+
 	mcu_mdio_pins_default: mcu-mdio1-pins-default {
 		pinctrl-single,pins = <
 			J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
@@ -186,6 +192,11 @@
 	status = "disabled";
 };
 
+&wkup_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
 &wkup_gpio1 {
 	status = "disabled";
 };
-- 
2.17.1

[PATCH v2 4/4] arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select pinmux

[Vaishnav Achath]

J721E common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_8 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index c11c092c1ce0..185de41cb2f1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -362,6 +362,12 @@
 			J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
 		>;
 	};
+
+	wkup_gpio_pins_default: wkup-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
+		>;
+	};
 };
 
 &wkup_uart0 {
@@ -419,6 +425,11 @@
 	status = "disabled";
 };
 
+&wkup_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
 &wkup_gpio1 {
 	status = "disabled";
 };
-- 
2.17.1

Re: [PATCH v2 0/4] arm64: dts: ti: j721e: Add HyperFlash support

[Vignesh Raghavendra]

Hi Vaishnav Achath,

On Sat, 13 May 2023 18:03:09 +0530, Vaishnav Achath wrote:
> This series adds hyperflash support for J721E. J721E SoC has HyperBus
> and OSPI controller muxed within the FSS subsystem and the J721E SoM
> has a 64 MiB S28 OSPI flash and a 64 MiB Hyperflash present which is
> muxed externally also.
> 
> Changelog:
> V1->V2:
>  * Address feedback in similar series:
>  https://lore.kernel.org/all/feddcd03-1848-b667-6a38-ae7c0f6ff160@ti.com/
>  * Add partitions information in Hyperflash node.
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/4] arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node
      commit: d93036b47f354b7acb95aad5c91e9becbe4e9f61
[2/4] arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node
      commit: 0979c0069cb669528d13818410de9f0dd41585f3
[3/4] arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux
      commit: be8be0d036b2fed1f705931ac3901077039b7496
[4/4] arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select pinmux
      commit: 58cd171af4d7e27525b1924b72100cba98d88d2a

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh