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From: alexis.lothore@bootlin.com
To: Andrew Lunn <andrew@lunn.ch>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Vladimir Oltean <olteanv@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Richard Cochran <richardcochran@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Russell King <linux@armlinux.org.uk>
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com,
	paul.arola@telus.com, scott.roberts@telus.com,
	"Marek Behún" <kabel@kernel.org>,
	"Alexis Lothoré" <alexis.lothore@bootlin.com>
Subject: [PATCH net-next v2 4/7] net: dsa: mv88e6xxx: add field to specify internal phys layout
Date: Fri, 19 May 2023 16:13:00 +0200	[thread overview]
Message-ID: <20230519141303.245235-5-alexis.lothore@bootlin.com> (raw)
In-Reply-To: <20230519141303.245235-1-alexis.lothore@bootlin.com>

From: Alexis Lothoré <alexis.lothore@bootlin.com>

mv88e6xxx currently assumes that switch equipped with internal phys have
those phys mapped contiguously starting from port 0 (see
mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
integrated PHYs available on ports 1 to 8
To properly support this offset, add a new field to allow specifying an
internal PHYs layout. If field is not set, default layout is assumed (start
at port 0)

Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
---
 drivers/net/dsa/mv88e6xxx/chip.c    | 4 +++-
 drivers/net/dsa/mv88e6xxx/chip.h    | 5 +++++
 drivers/net/dsa/mv88e6xxx/global2.c | 6 +++++-
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index c812e52bb5b7..2716d17c5c49 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -465,7 +465,9 @@ static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 
 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
 {
-	return port < chip->info->num_internal_phys;
+	return port >= chip->info->internal_phys_offset &&
+		port < chip->info->num_internal_phys +
+			chip->info->internal_phys_offset;
 }
 
 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index da6e1339f809..eca51946c100 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -167,6 +167,11 @@ struct mv88e6xxx_info {
 
 	/* Supports PTP */
 	bool ptp_support;
+
+	/* Internal PHY start index. 0 means that internal PHYs range starts at
+	 * port 0, 1 means internal PHYs range starts at port 1, etc
+	 */
+	unsigned int internal_phys_offset;
 };
 
 struct mv88e6xxx_atu_entry {
diff --git a/drivers/net/dsa/mv88e6xxx/global2.c b/drivers/net/dsa/mv88e6xxx/global2.c
index 615896893076..d460f7290012 100644
--- a/drivers/net/dsa/mv88e6xxx/global2.c
+++ b/drivers/net/dsa/mv88e6xxx/global2.c
@@ -1198,13 +1198,17 @@ int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
 {
 	int phy, irq;
 
-	for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
+	for (phy = chip->info->internal_phys_offset;
+	     phy <
+	     chip->info->num_internal_phys + chip->info->internal_phys_offset;
+	     phy++) {
 		irq = irq_find_mapping(chip->g2_irq.domain, phy);
 		if (irq < 0)
 			return irq;
 
 		bus->irq[chip->info->phy_base_addr + phy] = irq;
 	}
+
 	return 0;
 }
 
-- 
2.40.1


  parent reply	other threads:[~2023-05-19 14:13 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-19 14:12 [PATCH net-next v2 0/7] net: dsa: mv88e6xxx: add 88E6361 support alexis.lothore
2023-05-19 14:12 ` [PATCH net-next v2 1/7] dt-bindings: net: dsa: marvell: add MV88E6361 switch to compatibility list alexis.lothore
2023-05-20  2:54   ` Florian Fainelli
2023-05-19 14:12 ` [PATCH net-next v2 2/7] net: dsa: mv88e6xxx: pass directly chip structure to mv88e6xxx_phy_is_internal alexis.lothore
2023-05-19 14:36   ` Russell King (Oracle)
2023-05-20  2:54   ` Florian Fainelli
2023-05-19 14:12 ` [PATCH net-next v2 3/7] net: dsa: mv88e6xxx: use mv88e6xxx_phy_is_internal in mv88e6xxx_port_ppu_updates alexis.lothore
2023-05-19 14:37   ` Russell King (Oracle)
2023-05-20  2:54   ` Florian Fainelli
2023-05-19 14:13 ` alexis.lothore [this message]
2023-05-19 16:11   ` [PATCH net-next v2 4/7] net: dsa: mv88e6xxx: add field to specify internal phys layout Andrew Lunn
2023-05-19 14:13 ` [PATCH net-next v2 5/7] net: dsa: mv88e6xxx: fix 88E6393X family " alexis.lothore
2023-05-19 16:12   ` Andrew Lunn
2023-05-20  2:55   ` Florian Fainelli
2023-05-19 14:13 ` [PATCH net-next v2 6/7] net: dsa: mv88e6xxx: pass mv88e6xxx_chip structure to port_max_speed_mode alexis.lothore
2023-05-20  2:56   ` Florian Fainelli
2023-05-19 14:13 ` [PATCH net-next v2 7/7] net: dsa: mv88e6xxx: enable support for 88E6361 switch alexis.lothore
2023-05-19 14:43   ` Russell King (Oracle)
2023-05-22  8:15     ` Alexis Lothoré
2023-05-22 12:19       ` Andrew Lunn
2023-05-22 12:26         ` Alexis Lothoré
2023-05-19 16:21   ` Andrew Lunn

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