Re: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock

[David Epping <david.epping@missinglinkelectronics.com>]

On Sun, May 21, 2023 at 04:43:56PM +0300, Vladimir Oltean wrote:
> Not only bit 11 is reserved for VSC8530, but it's also read-only, so it
> should not matter what is written there.

I agree and am ok with removing the PHY ID condition.

> Since vsc85xx_rgmii_enable_rx_clk() and vsc85xx_rgmii_set_skews() write
> to the same register, would it not make sense to combine the two into a
> single phy_modify_paged() call, and to zeroize bit 11 as part of that?

Since we found an explanation why the current driver works in some
setups (U-Boot), I would go with the Microchip support statement, that
writing bit 11 to 0 is required in all modes.
It would thus stay a separate function, called without a phy mode
condition, and not be combined with the RGMII skew setting function.

> The other caller of vsc85xx_rgmii_set_skews(), VSC8572, unfortunately
> does not document bit 11 at all - it doesn't say if it's read-only or not.
> We could conditionally include the VSC8502_RGMII_RX_CLK_DISABLE bit in the
> "mask" argument of phy_modify_paged() based on rgmii_cntl == VSC8502_RGMII_CNTL,
> such as to exclude VSC8572.

Because of the above, I would still call from vsc85xx_default_config(),
so not for the PHYs where bit 11 is not documented.

> What do you think?

If you agree to the above, should the function be named
vsc85xx_enable_rx_clk() or rather vsc8502_enable_rx_clk()?
It is called for more than just VSC8502, but not for all of the PHYs
the driver supports.
The same is true for the existing vsc85xx_default_config(), however.
I don't have a real preference.