From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org, broonie@kernel.org
Cc: Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Rob Herring <robh@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
kvmarm@lists.linux.dev, coresight@lists.linaro.org,
linux-kernel@vger.kernel.org
Subject: [PATCH V3 11/14] arm64/sysreg: Convert TRBSR_EL1 register to automatic generation
Date: Wed, 14 Jun 2023 12:29:46 +0530 [thread overview]
Message-ID: <20230614065949.146187-12-anshuman.khandual@arm.com> (raw)
In-Reply-To: <20230614065949.146187-1-anshuman.khandual@arm.com>
This converts TRBSR_EL1 register to automatic generation without
causing any functional change.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/sysreg.h | 12 ------------
arch/arm64/tools/sysreg | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 72765f0df4c5..0c144c276706 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -241,24 +241,12 @@
/*** End of Statistical Profiling Extension ***/
-#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
-#define TRBSR_EL1_EC_MASK GENMASK(31, 26)
-#define TRBSR_EL1_EC_SHIFT 26
-#define TRBSR_EL1_IRQ BIT(22)
-#define TRBSR_EL1_TRG BIT(21)
-#define TRBSR_EL1_WRAP BIT(20)
-#define TRBSR_EL1_EA BIT(18)
-#define TRBSR_EL1_S BIT(17)
-#define TRBSR_EL1_MSS_MASK GENMASK(15, 0)
-#define TRBSR_EL1_MSS_SHIFT 0
#define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
#define TRBSR_EL1_BSC_SHIFT 0
-#define TRBSR_EL1_FSC_MASK GENMASK(5, 0)
-#define TRBSR_EL1_FSC_SHIFT 0
#define TRBMAR_EL1_SH_MASK GENMASK(9, 8)
#define TRBMAR_EL1_SH_SHIFT 8
#define TRBMAR_EL1_Attr_MASK GENMASK(7, 0)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c58731f69467..6d12980f01c7 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2227,3 +2227,19 @@ Sysreg TRBBASER_EL1 3 0 9 11 2
Field 63:12 BASE
Res0 11:0
EndSysreg
+
+Sysreg TRBSR_EL1 3 0 9 11 3
+Res0 63:56
+Field 55:32 MSS2
+Field 31:26 EC
+Res0 25:24
+Field 23 DAT
+Field 22 IRQ
+Field 21 TRG
+Field 20 WRAP
+Res0 19
+Field 18 EA
+Field 17 S
+Res0 16
+Field 15:0 MSS
+EndSysreg
--
2.25.1
next prev parent reply other threads:[~2023-06-14 7:01 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 6:59 [PATCH V3 00/14] arm64/sysreg: Convert TRBE registers " Anshuman Khandual
2023-06-14 6:59 ` [PATCH V3 01/14] arm64/sysreg: Rename TRBLIMITR_EL1 fields per auto-gen tools format Anshuman Khandual
2023-06-14 6:59 ` [PATCH V3 02/14] arm64/sysreg: Rename TRBPTR_EL1 " Anshuman Khandual
2023-06-14 6:59 ` [PATCH V3 03/14] arm64/sysreg: Rename TRBBASER_EL1 " Anshuman Khandual
2023-06-14 6:59 ` [PATCH V3 04/14] arm64/sysreg: Rename TRBSR_EL1 " Anshuman Khandual
2023-06-14 6:59 ` [PATCH V3 05/14] arm64/sysreg: Rename TRBMAR_EL1 " Anshuman Khandual
2023-06-14 6:59 ` [PATCH V3 06/14] arm64/sysreg: Rename TRBTRG_EL1 " Anshuman Khandual
2023-06-14 6:59 ` [PATCH V3 07/14] arm64/sysreg: Rename TRBIDR_EL1 " Anshuman Khandual
2023-06-14 6:59 ` [PATCH V3 08/14] arm64/sysreg: Convert TRBLIMITR_EL1 register to automatic generation Anshuman Khandual
2023-06-14 11:39 ` Mark Brown
2023-06-14 6:59 ` [PATCH V3 09/14] arm64/sysreg: Convert TRBPTR_EL1 " Anshuman Khandual
2023-06-14 11:40 ` Mark Brown
2023-06-14 6:59 ` [PATCH V3 10/14] arm64/sysreg: Convert TRBBASER_EL1 " Anshuman Khandual
2023-06-14 11:41 ` Mark Brown
2023-06-14 6:59 ` Anshuman Khandual [this message]
2023-06-14 11:43 ` [PATCH V3 11/14] arm64/sysreg: Convert TRBSR_EL1 " Mark Brown
2023-06-14 6:59 ` [PATCH V3 12/14] arm64/sysreg: Convert TRBMAR_EL1 " Anshuman Khandual
2023-06-14 11:44 ` Mark Brown
2023-06-14 6:59 ` [PATCH V3 13/14] arm64/sysreg: Convert TRBTRG_EL1 " Anshuman Khandual
2023-06-14 11:44 ` Mark Brown
2023-06-14 6:59 ` [PATCH V3 14/14] arm64/sysreg: Convert TRBIDR_EL1 " Anshuman Khandual
2023-06-14 11:45 ` Mark Brown
2023-06-14 11:54 ` [PATCH V3 00/14] arm64/sysreg: Convert TRBE registers " Suzuki K Poulose
2023-06-14 17:19 ` Catalin Marinas
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