* [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz
@ 2023-06-14 13:47 Alibek Omarov
2023-06-20 12:52 ` Alibek Omarov
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Alibek Omarov @ 2023-06-14 13:47 UTC (permalink / raw)
To: linux-rockchip
Cc: a1ba.omarov, Michael Turquette, Stephen Boyd, Heiko Stuebner,
Sascha Hauer, linux-clk, linux-arm-kernel, linux-kernel
This patch adds PLL setting for not so common resolution as 1920x720-50.00,
which can be set using 2500 horizontal signals and 808 vertical.
Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
---
drivers/clk/rockchip/clk-rk3568.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index f85902e2590c..5dae960af4ce 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
+ RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz
2023-06-14 13:47 [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz Alibek Omarov
@ 2023-06-20 12:52 ` Alibek Omarov
2023-06-26 9:38 ` Sascha Hauer
2023-06-26 10:57 ` Heiko Stuebner
2 siblings, 0 replies; 4+ messages in thread
From: Alibek Omarov @ 2023-06-20 12:52 UTC (permalink / raw)
To: linux-rockchip
Cc: Michael Turquette, Stephen Boyd, Heiko Stuebner, Sascha Hauer,
linux-clk, linux-arm-kernel, linux-kernel
bump
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz
2023-06-14 13:47 [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz Alibek Omarov
2023-06-20 12:52 ` Alibek Omarov
@ 2023-06-26 9:38 ` Sascha Hauer
2023-06-26 10:57 ` Heiko Stuebner
2 siblings, 0 replies; 4+ messages in thread
From: Sascha Hauer @ 2023-06-26 9:38 UTC (permalink / raw)
To: Alibek Omarov
Cc: linux-rockchip, Michael Turquette, Stephen Boyd, Heiko Stuebner,
linux-clk, linux-arm-kernel, linux-kernel
On Wed, Jun 14, 2023 at 04:47:16PM +0300, Alibek Omarov wrote:
> This patch adds PLL setting for not so common resolution as 1920x720-50.00,
> which can be set using 2500 horizontal signals and 808 vertical.
>
> Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> drivers/clk/rockchip/clk-rk3568.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
> index f85902e2590c..5dae960af4ce 100644
> --- a/drivers/clk/rockchip/clk-rk3568.c
> +++ b/drivers/clk/rockchip/clk-rk3568.c
> @@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
> RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
> RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
> RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
> + RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
refdiv = 1
fbdiv = 101
postdiv1 = 6
postdiv2 = 4
((24000000/1)*101)/6/4 = 101000000
Ok.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz
2023-06-14 13:47 [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz Alibek Omarov
2023-06-20 12:52 ` Alibek Omarov
2023-06-26 9:38 ` Sascha Hauer
@ 2023-06-26 10:57 ` Heiko Stuebner
2 siblings, 0 replies; 4+ messages in thread
From: Heiko Stuebner @ 2023-06-26 10:57 UTC (permalink / raw)
To: linux-rockchip, Alibek Omarov
Cc: Heiko Stuebner, Sascha Hauer, Michael Turquette, Stephen Boyd,
linux-kernel, linux-arm-kernel, linux-clk
On Wed, 14 Jun 2023 16:47:16 +0300, Alibek Omarov wrote:
> This patch adds PLL setting for not so common resolution as 1920x720-50.00,
> which can be set using 2500 horizontal signals and 808 vertical.
>
>
Applied, thanks!
[1/1] clk: rockchip: rk3568: Add PLL rate for 101MHz
commit: 294580c9b921946f0f6b964326ccbf2d1cd78f7a
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-06-26 10:58 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2023-06-14 13:47 [PATCH] clk: rockchip: rk3568: Add PLL rate for 101MHz Alibek Omarov
2023-06-20 12:52 ` Alibek Omarov
2023-06-26 9:38 ` Sascha Hauer
2023-06-26 10:57 ` Heiko Stuebner
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