From: Conor Dooley <conor@kernel.org>
To: Evan Green <evan@rivosinc.com>
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
Simon Hosie <shosie@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Andy Chiu <andy.chiu@sifive.com>,
Anup Patel <apatel@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
Greentime Hu <greentime.hu@sifive.com>,
Guo Ren <guoren@kernel.org>,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Heiko Stuebner <heiko@sntech.de>,
Jisheng Zhang <jszhang@kernel.org>,
Jonathan Corbet <corbet@lwn.net>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
Li Zhengyu <lizhengyu3@huawei.com>,
Masahiro Yamada <masahiroy@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Randy Dunlap <rdunlap@infradead.org>,
Samuel Holland <samuel@sholland.org>,
Sia Jee Heng <jeeheng.sia@starfivetech.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Xianting Tian <xianting.tian@linux.alibaba.com>,
Yangyu Chen <cyy@cyyself.name>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH 0/2] RISC-V: Probe for misaligned access speed
Date: Sat, 24 Jun 2023 11:08:03 +0100 [thread overview]
Message-ID: <20230624-tycoon-pliable-325806e73a11@spud> (raw)
In-Reply-To: <20230623222016.3742145-1-evan@rivosinc.com>
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On Fri, Jun 23, 2023 at 03:20:14PM -0700, Evan Green wrote:
>
> The current setting for the hwprobe bit indicating misaligned access
> speed is controlled by a vendor-specific feature probe function. This is
> essentially a per-SoC table we have to maintain on behalf of each vendor
> going forward. Let's convert that instead to something we detect at
> runtime.
>
> We have two assembly routines at the heart of our probe: one that
> does a bunch of word-sized accesses (without aligning its input buffer),
> and the other that does byte accesses. If we can move a larger number of
> bytes using misaligned word accesses than we can with the same amount of
> time doing byte accesses, then we can declare misaligned accesses as
> "fast".
>
> The tradeoff of reducing this maintenance burden is boot time. We spend
> 4-6 jiffies per core doing this measurement (0-2 on jiffie edge
> alignment, and 4 on measurement). The timing loop was based on
> raid6_choose_gen(), which uses (16+1)*N jiffies (where N is the number
> of algorithms). On my THead C906, I found measurements to be stable
> across several reboots, and looked like this:
>
> [ 0.047582] cpu0: Unaligned word copy 1728 MB/s, byte copy 402 MB/s, misaligned accesses are fast
>
> I don't have a machine where misaligned accesses are slow, but I'd be
> interested to see the results of booting this series if someone did.
Can you elaborate on "results" please? Otherwise,
[ 0.333110] smp: Bringing up secondary CPUs ...
[ 0.370794] cpu1: Unaligned word copy 2 MB/s, byte copy 231 MB/s, misaligned accesses are slow
[ 0.411368] cpu2: Unaligned word copy 2 MB/s, byte copy 231 MB/s, misaligned accesses are slow
[ 0.451947] cpu3: Unaligned word copy 2 MB/s, byte copy 231 MB/s, misaligned accesses are slow
[ 0.462628] smp: Brought up 1 node, 4 CPUs
[ 0.631464] cpu0: Unaligned word copy 2 MB/s, byte copy 229 MB/s, misaligned accesses are slow
btw, why the mixed usage of "unaligned" and misaligned"?
Cheers,
Conor.
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next prev parent reply other threads:[~2023-06-24 10:08 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-23 22:20 Evan Green
2023-06-23 22:20 ` [PATCH 1/2] RISC-V: Probe for unaligned " Evan Green
2023-06-25 21:42 ` David Laight
2023-06-26 14:14 ` Conor Dooley
2023-06-27 19:11 ` Evan Green
2023-06-29 14:03 ` Conor Dooley
2023-06-29 23:10 ` Evan Green
2023-06-26 21:42 ` Jessica Clarke
2023-06-27 19:11 ` Evan Green
2023-06-29 12:05 ` David Laight
2023-06-29 23:09 ` Evan Green
2023-06-30 8:29 ` David Laight
2023-06-23 22:20 ` [PATCH 2/2] RISC-V: alternative: Remove feature_probe_func Evan Green
2023-06-26 13:07 ` Conor Dooley
2023-06-30 21:57 ` Evan Green
2023-06-24 10:08 ` Conor Dooley [this message]
2023-06-26 19:48 ` [PATCH 0/2] RISC-V: Probe for misaligned access speed Evan Green
2023-06-24 10:22 ` Yangyu Chen
2023-06-26 9:24 ` David Laight
2023-06-26 19:49 ` Evan Green
2023-06-26 19:48 ` Evan Green
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