From: Yangtao Li <frank.li@vivo.com>
To: Moritz Fischer <mdf@kernel.org>, Wu Hao <hao.wu@intel.com>,
Xu Yilun <yilun.xu@intel.com>, Tom Rix <trix@redhat.com>
Cc: Yangtao Li <frank.li@vivo.com>,
linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/8] fpga: bridge: Convert to devm_platform_ioremap_resource()
Date: Wed, 5 Jul 2023 17:46:48 +0800 [thread overview]
Message-ID: <20230705094655.44753-1-frank.li@vivo.com> (raw)
Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li <frank.li@vivo.com>
---
drivers/fpga/altera-freeze-bridge.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/fpga/altera-freeze-bridge.c b/drivers/fpga/altera-freeze-bridge.c
index 445f4b011167..bb6b02ec2d21 100644
--- a/drivers/fpga/altera-freeze-bridge.c
+++ b/drivers/fpga/altera-freeze-bridge.c
@@ -213,14 +213,12 @@ static int altera_freeze_br_probe(struct platform_device *pdev)
void __iomem *base_addr;
struct altera_freeze_br_data *priv;
struct fpga_bridge *br;
- struct resource *res;
u32 status, revision;
if (!np)
return -ENODEV;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base_addr = devm_ioremap_resource(dev, res);
+ base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
--
2.39.0
next reply other threads:[~2023-07-05 9:47 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-05 9:46 Yangtao Li [this message]
2023-07-05 9:46 ` [PATCH 2/8] fpga: fpga-mgr: altera-pr-ip: " Yangtao Li
2023-07-10 8:30 ` Xu Yilun
2023-07-05 9:46 ` [PATCH 3/8] fpga: dfl-fme-mgr: " Yangtao Li
2023-07-10 8:39 ` Xu Yilun
2023-07-05 9:46 ` [PATCH 4/8] fpga: socfpga-a10: " Yangtao Li
2023-07-10 8:36 ` Xu Yilun
2023-07-05 9:46 ` [PATCH 5/8] fpga: xilinx-pr-decoupler: " Yangtao Li
2023-07-07 4:55 ` Michal Simek
2023-07-10 8:42 ` Xu Yilun
2023-07-05 9:46 ` [PATCH 6/8] fpga: fpga-mgr: socfpga: " Yangtao Li
2023-07-10 8:47 ` Xu Yilun
2023-07-05 9:46 ` [PATCH 7/8] fpga: fpga-mgr: ts73xx: " Yangtao Li
2023-07-10 8:52 ` Xu Yilun
2023-07-05 9:46 ` [PATCH 8/8] fpga: zynq-fpga: " Yangtao Li
2023-07-07 4:55 ` Michal Simek
2023-07-10 8:54 ` Xu Yilun
2023-07-10 8:38 ` [PATCH 1/8] fpga: bridge: " Xu Yilun
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