* [PATCH v4 1/3] peci: cpu: Add Intel Sapphire Rapids support @ 2023-07-25 10:43 Naresh Solanki 2023-07-25 10:43 ` [PATCH v4 2/3] hwmon: (peci/cputemp) " Naresh Solanki 2023-07-25 10:43 ` [PATCH v4 3/3] hwmon: (peci/dimmtemp) Add " Naresh Solanki 0 siblings, 2 replies; 4+ messages in thread From: Naresh Solanki @ 2023-07-25 10:43 UTC (permalink / raw) To: linux-kernel, linux-hwmon, iwona.winiarska, linux, jdelvare Cc: Naresh Solanki, Patrick Rudolph, openbmc Add support for detection of Intel Sapphire Rapids processor based on CPU family & model. Sapphire Rapids Xeon processors with the family set to 6 and the model set to INTEL_FAM6_SAPPHIRERAPIDS_X. The data field for this entry is "spr". Tested the patch series with AST2600 BMC with 4S Intel Sapphire Rapids processors & verified by reading cpu & dimm temperature. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-by: Iwona Winiarska <iwona.winiarska@intel.com> --- Changes in V3: - Move spr entry at end of struct peci_cpu_device_ids - Mention test with the patch. Changes in V2: - Refactored from previous patchset as seperate patch based on subsystem. --- drivers/peci/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/peci/cpu.c b/drivers/peci/cpu.c index de4a7b3e5966..bd990acd92b8 100644 --- a/drivers/peci/cpu.c +++ b/drivers/peci/cpu.c @@ -323,6 +323,11 @@ static const struct peci_device_id peci_cpu_device_ids[] = { .model = INTEL_FAM6_ICELAKE_D, .data = "icxd", }, + { /* Sapphire Rapids Xeon */ + .family = 6, + .model = INTEL_FAM6_SAPPHIRERAPIDS_X, + .data = "spr", + }, { } }; MODULE_DEVICE_TABLE(peci, peci_cpu_device_ids); base-commit: 55612007f16b5d7b1fb83a7b0f5bb686829db7c7 -- 2.41.0 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v4 2/3] hwmon: (peci/cputemp) Add Intel Sapphire Rapids support 2023-07-25 10:43 [PATCH v4 1/3] peci: cpu: Add Intel Sapphire Rapids support Naresh Solanki @ 2023-07-25 10:43 ` Naresh Solanki 2023-07-25 10:43 ` [PATCH v4 3/3] hwmon: (peci/dimmtemp) Add " Naresh Solanki 1 sibling, 0 replies; 4+ messages in thread From: Naresh Solanki @ 2023-07-25 10:43 UTC (permalink / raw) To: linux-kernel, linux-hwmon, iwona.winiarska, linux, jdelvare Cc: Patrick Rudolph, Naresh Solanki From: Patrick Rudolph <patrick.rudolph@9elements.com> Add support to read DTS for reading Intel Sapphire Rapids platform. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Iwona Winiarska <iwona.winiarska@intel.com> --- Chagnes in V3: - Update Acked-by in commit message. Changes in V2: - Refactored from previous patchset as seperate patch based on subsystem. --- drivers/hwmon/peci/cputemp.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/hwmon/peci/cputemp.c b/drivers/hwmon/peci/cputemp.c index e5b65a382772..a812c15948d9 100644 --- a/drivers/hwmon/peci/cputemp.c +++ b/drivers/hwmon/peci/cputemp.c @@ -363,6 +363,7 @@ static int init_core_mask(struct peci_cputemp *priv) switch (peci_dev->info.model) { case INTEL_FAM6_ICELAKE_X: case INTEL_FAM6_ICELAKE_D: + case INTEL_FAM6_SAPPHIRERAPIDS_X: ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev, reg->func, reg->offset + 4, &data); if (ret) @@ -531,6 +532,13 @@ static struct resolved_cores_reg resolved_cores_reg_icx = { .offset = 0xd0, }; +static struct resolved_cores_reg resolved_cores_reg_spr = { + .bus = 31, + .dev = 30, + .func = 6, + .offset = 0x80, +}; + static const struct cpu_info cpu_hsx = { .reg = &resolved_cores_reg_hsx, .min_peci_revision = 0x33, @@ -549,6 +557,12 @@ static const struct cpu_info cpu_icx = { .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree, }; +static const struct cpu_info cpu_spr = { + .reg = &resolved_cores_reg_spr, + .min_peci_revision = 0x40, + .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree, +}; + static const struct auxiliary_device_id peci_cputemp_ids[] = { { .name = "peci_cpu.cputemp.hsx", @@ -574,6 +588,10 @@ static const struct auxiliary_device_id peci_cputemp_ids[] = { .name = "peci_cpu.cputemp.icxd", .driver_data = (kernel_ulong_t)&cpu_icx, }, + { + .name = "peci_cpu.cputemp.spr", + .driver_data = (kernel_ulong_t)&cpu_spr, + }, { } }; MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids); -- 2.41.0 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v4 3/3] hwmon: (peci/dimmtemp) Add Sapphire Rapids support 2023-07-25 10:43 [PATCH v4 1/3] peci: cpu: Add Intel Sapphire Rapids support Naresh Solanki 2023-07-25 10:43 ` [PATCH v4 2/3] hwmon: (peci/cputemp) " Naresh Solanki @ 2023-07-25 10:43 ` Naresh Solanki 2023-07-26 20:22 ` Winiarska, Iwona 1 sibling, 1 reply; 4+ messages in thread From: Naresh Solanki @ 2023-07-25 10:43 UTC (permalink / raw) To: linux-kernel, linux-hwmon, iwona.winiarska, linux, jdelvare Cc: Patrick Rudolph, Naresh Solanki From: Patrick Rudolph <patrick.rudolph@9elements.com> Extend the functionality of hwmon (peci/dimmtemp) for Sapphire Rapids platform. Add the corresponding Sapphire Rapids ID and threshold code. The patch has been tested on a 4S system with 64 DIMMs installed. Verified read of DIMM temperature thresholds & temperature. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Acked-by: Guenter Roeck <linux@roeck-us.net> --- Changes in V4: - Instead of using hard coded dimm temperature threshold, read from mmio offset. - Change CHAN_RANK_MAX_ON_SPR to 8 - Restore #define CHAN_RANK_MAX to previous assignment. - Update commit message. Changes in V3: - Update Acked-by in commit message. Changes in V2: - Update subject. --- drivers/hwmon/peci/dimmtemp.c | 50 +++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c index ce89da3937a0..5ca4d04e4b14 100644 --- a/drivers/hwmon/peci/dimmtemp.c +++ b/drivers/hwmon/peci/dimmtemp.c @@ -30,6 +30,8 @@ #define DIMM_IDX_MAX_ON_ICX 2 #define CHAN_RANK_MAX_ON_ICXD 4 #define DIMM_IDX_MAX_ON_ICXD 2 +#define CHAN_RANK_MAX_ON_SPR 8 +#define DIMM_IDX_MAX_ON_SPR 2 #define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX #define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX @@ -534,6 +536,43 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u return 0; } +static int +read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data) +{ + u32 reg_val; + u64 offset; + int ret; + u8 dev; + + ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4, ®_val); + if (ret || !(reg_val & BIT(31))) + return -ENODATA; /* Use default or previous value */ + + ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0, ®_val); + if (ret) + return -ENODATA; /* Use default or previous value */ + + /* + * Device 26, Offset 219a8: IMC 0 channel 0 -> rank 0 + * Device 26, Offset 299a8: IMC 0 channel 1 -> rank 1 + * Device 27, Offset 219a8: IMC 1 channel 0 -> rank 2 + * Device 27, Offset 299a8: IMC 1 channel 1 -> rank 3 + * Device 28, Offset 219a8: IMC 2 channel 0 -> rank 4 + * Device 28, Offset 299a8: IMC 2 channel 1 -> rank 5 + * Device 29, Offset 219a8: IMC 3 channel 0 -> rank 6 + * Device 29, Offset 299a8: IMC 3 channel 1 -> rank 7 + */ + dev = 26 + chan_rank / 2; + offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000; + + ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val), + dev, 0, offset, data); + if (ret) + return ret; + + return 0; +} + static const struct dimm_info dimm_hsx = { .chan_rank_max = CHAN_RANK_MAX_ON_HSX, .dimm_idx_max = DIMM_IDX_MAX_ON_HSX, @@ -576,6 +615,13 @@ static const struct dimm_info dimm_icxd = { .read_thresholds = &read_thresholds_icx, }; +static const struct dimm_info dimm_spr = { + .chan_rank_max = CHAN_RANK_MAX_ON_SPR, + .dimm_idx_max = DIMM_IDX_MAX_ON_SPR, + .min_peci_revision = 0x40, + .read_thresholds = &read_thresholds_spr, +}; + static const struct auxiliary_device_id peci_dimmtemp_ids[] = { { .name = "peci_cpu.dimmtemp.hsx", @@ -601,6 +647,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = { .name = "peci_cpu.dimmtemp.icxd", .driver_data = (kernel_ulong_t)&dimm_icxd, }, + { + .name = "peci_cpu.dimmtemp.spr", + .driver_data = (kernel_ulong_t)&dimm_spr, + }, { } }; MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids); -- 2.41.0 ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v4 3/3] hwmon: (peci/dimmtemp) Add Sapphire Rapids support 2023-07-25 10:43 ` [PATCH v4 3/3] hwmon: (peci/dimmtemp) Add " Naresh Solanki @ 2023-07-26 20:22 ` Winiarska, Iwona 0 siblings, 0 replies; 4+ messages in thread From: Winiarska, Iwona @ 2023-07-26 20:22 UTC (permalink / raw) To: linux, linux-hwmon, linux-kernel, Solanki, Naresh, jdelvare Cc: Rudolph, Patrick On Tue, 2023-07-25 at 12:43 +0200, Naresh Solanki wrote: > From: Patrick Rudolph <patrick.rudolph@9elements.com> > > Extend the functionality of hwmon (peci/dimmtemp) for Sapphire Rapids > platform. > > Add the corresponding Sapphire Rapids ID and threshold code. > > The patch has been tested on a 4S system with 64 DIMMs installed. > Verified read of DIMM temperature thresholds & temperature. > > Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> > Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> > Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Iwona Winiarska <iwona.winiarska@intel.com> I'll apply it to peci-next. Thanks -Iwona > --- > Changes in V4: > - Instead of using hard coded dimm temperature threshold, read from mmio > offset. > - Change CHAN_RANK_MAX_ON_SPR to 8 > - Restore #define CHAN_RANK_MAX to previous assignment. > - Update commit message. > Changes in V3: > - Update Acked-by in commit message. > Changes in V2: > - Update subject. > --- > drivers/hwmon/peci/dimmtemp.c | 50 +++++++++++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c > index ce89da3937a0..5ca4d04e4b14 100644 > --- a/drivers/hwmon/peci/dimmtemp.c > +++ b/drivers/hwmon/peci/dimmtemp.c > @@ -30,6 +30,8 @@ > #define DIMM_IDX_MAX_ON_ICX 2 > #define CHAN_RANK_MAX_ON_ICXD 4 > #define DIMM_IDX_MAX_ON_ICXD 2 > +#define CHAN_RANK_MAX_ON_SPR 8 > +#define DIMM_IDX_MAX_ON_SPR 2 > > #define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX > #define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX > @@ -534,6 +536,43 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int > dimm_order, int chan_rank, u > return 0; > } > > +static int > +read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int > chan_rank, u32 *data) > +{ > + u32 reg_val; > + u64 offset; > + int ret; > + u8 dev; > + > + ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4, > ®_val); > + if (ret || !(reg_val & BIT(31))) > + return -ENODATA; /* Use default or previous value */ > + > + ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0, > ®_val); > + if (ret) > + return -ENODATA; /* Use default or previous value */ > + > + /* > + * Device 26, Offset 219a8: IMC 0 channel 0 -> rank 0 > + * Device 26, Offset 299a8: IMC 0 channel 1 -> rank 1 > + * Device 27, Offset 219a8: IMC 1 channel 0 -> rank 2 > + * Device 27, Offset 299a8: IMC 1 channel 1 -> rank 3 > + * Device 28, Offset 219a8: IMC 2 channel 0 -> rank 4 > + * Device 28, Offset 299a8: IMC 2 channel 1 -> rank 5 > + * Device 29, Offset 219a8: IMC 3 channel 0 -> rank 6 > + * Device 29, Offset 299a8: IMC 3 channel 1 -> rank 7 > + */ > + dev = 26 + chan_rank / 2; > + offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000; > + > + ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), > GET_CPU_BUS(reg_val), > + dev, 0, offset, data); > + if (ret) > + return ret; > + > + return 0; > +} > + > static const struct dimm_info dimm_hsx = { > .chan_rank_max = CHAN_RANK_MAX_ON_HSX, > .dimm_idx_max = DIMM_IDX_MAX_ON_HSX, > @@ -576,6 +615,13 @@ static const struct dimm_info dimm_icxd = { > .read_thresholds = &read_thresholds_icx, > }; > > +static const struct dimm_info dimm_spr = { > + .chan_rank_max = CHAN_RANK_MAX_ON_SPR, > + .dimm_idx_max = DIMM_IDX_MAX_ON_SPR, > + .min_peci_revision = 0x40, > + .read_thresholds = &read_thresholds_spr, > +}; > + > static const struct auxiliary_device_id peci_dimmtemp_ids[] = { > { > .name = "peci_cpu.dimmtemp.hsx", > @@ -601,6 +647,10 @@ static const struct auxiliary_device_id > peci_dimmtemp_ids[] = { > .name = "peci_cpu.dimmtemp.icxd", > .driver_data = (kernel_ulong_t)&dimm_icxd, > }, > + { > + .name = "peci_cpu.dimmtemp.spr", > + .driver_data = (kernel_ulong_t)&dimm_spr, > + }, > { } > }; > MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids); ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-07-26 20:22 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-07-25 10:43 [PATCH v4 1/3] peci: cpu: Add Intel Sapphire Rapids support Naresh Solanki 2023-07-25 10:43 ` [PATCH v4 2/3] hwmon: (peci/cputemp) " Naresh Solanki 2023-07-25 10:43 ` [PATCH v4 3/3] hwmon: (peci/dimmtemp) Add " Naresh Solanki 2023-07-26 20:22 ` Winiarska, Iwona
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