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From: Linu Cherian <lcherian@marvell.com>
To: <suzuki.poulose@arm.com>, <mike.leach@linaro.org>,
	<james.clark@arm.com>, <leo.yan@linaro.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<coresight@lists.linaro.org>, <linux-kernel@vger.kernel.org>,
	<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<conor+dt@kernel.org>, <devicetree@vger.kernel.org>,
	<sgoutham@marvell.com>, <gcherian@marvell.com>,
	Linu Cherian <lcherian@marvell.com>
Subject: [RFC PATCH v3 3/7] coresight: core: Add provision for panic callbacks
Date: Mon, 4 Sep 2023 10:35:43 +0530	[thread overview]
Message-ID: <20230904050548.28047-4-lcherian@marvell.com> (raw)
In-Reply-To: <20230904050548.28047-1-lcherian@marvell.com>

Panic callback handlers allows coresight device drivers to sync
relevant trace data and trace metadata to reserved memory
regions so that they can be retrieved later in the subsequent
boot or in the crashdump kernel.

Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
 drivers/hwtracing/coresight/coresight-core.c | 32 ++++++++++++++++++++
 include/linux/coresight.h                    | 12 ++++++++
 2 files changed, 44 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 118fcf27854d..de4e3947c8e5 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -20,6 +20,7 @@
 #include <linux/of_platform.h>
 #include <linux/delay.h>
 #include <linux/pm_runtime.h>
+#include <linux/panic_notifier.h>
 
 #include "coresight-etm-perf.h"
 #include "coresight-priv.h"
@@ -1800,6 +1801,31 @@ struct bus_type coresight_bustype = {
 	.name	= "coresight",
 };
 
+static int coresight_panic_sync(struct device *dev, void *data)
+{
+
+	struct coresight_device *csdev = container_of(dev, struct coresight_device, dev);
+
+	/* Run through panic sync handlers for all enabled devices */
+	if (csdev->enable && panic_ops(csdev))
+		panic_ops(csdev)->sync(csdev);
+
+	return 0;
+}
+
+static int coresight_panic_cb(struct notifier_block *self,
+			       unsigned long v, void *p)
+{
+	bus_for_each_dev(&coresight_bustype, NULL, NULL,
+				 coresight_panic_sync);
+
+	return 0;
+}
+
+static struct notifier_block coresight_notifier = {
+	.notifier_call = coresight_panic_cb,
+};
+
 static int __init coresight_init(void)
 {
 	int ret;
@@ -1812,6 +1838,10 @@ static int __init coresight_init(void)
 	if (ret)
 		goto exit_bus_unregister;
 
+	/* Register function to be called for panic */
+	ret = atomic_notifier_chain_register(&panic_notifier_list,
+					     &coresight_notifier);
+
 	/* initialise the coresight syscfg API */
 	ret = cscfg_init();
 	if (!ret)
@@ -1826,6 +1856,8 @@ static int __init coresight_init(void)
 static void __exit coresight_exit(void)
 {
 	cscfg_exit();
+	atomic_notifier_chain_unregister(&panic_notifier_list,
+					     &coresight_notifier);
 	etm_perf_exit();
 	bus_unregister(&coresight_bustype);
 }
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index bf70987240e4..09978ea6abe1 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -299,6 +299,7 @@ enum cs_mode {
 #define link_ops(csdev)		csdev->ops->link_ops
 #define helper_ops(csdev)	csdev->ops->helper_ops
 #define ect_ops(csdev)		csdev->ops->ect_ops
+#define panic_ops(csdev)	csdev->ops->panic_ops
 
 /**
  * struct coresight_ops_sink - basic operations for a sink
@@ -368,11 +369,22 @@ struct coresight_ops_helper {
 	int (*disable)(struct coresight_device *csdev, void *data);
 };
 
+
+/**
+ * struct coresight_ops_panic - Generic device ops for panic handing
+ *
+ * @sync	: Sync the device register state/trace data
+ */
+struct coresight_ops_panic {
+	int (*sync)(struct coresight_device *csdev);
+};
+
 struct coresight_ops {
 	const struct coresight_ops_sink *sink_ops;
 	const struct coresight_ops_link *link_ops;
 	const struct coresight_ops_source *source_ops;
 	const struct coresight_ops_helper *helper_ops;
+	const struct coresight_ops_panic *panic_ops;
 };
 
 #if IS_ENABLED(CONFIG_CORESIGHT)
-- 
2.41.0


  parent reply	other threads:[~2023-09-04  5:06 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-04  5:05 [RFC PATCH v3 0/8] Coresight for Kernel panic and watchdog reset Linu Cherian
2023-09-04  5:05 ` [RFC PATCH v3 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property Linu Cherian
2023-09-04  6:23   ` Rob Herring
2023-09-09 14:12     ` [EXT] " Linu Cherian
2023-09-04  8:26   ` Suzuki K Poulose
2023-09-05 15:35     ` Rob Herring
2023-09-09 14:06     ` [EXT] " Linu Cherian
2023-09-04  5:05 ` [RFC PATCH v3 2/7] coresight: tmc-etr: Add support to use reserved trace memory Linu Cherian
2023-09-04  5:05 ` Linu Cherian [this message]
2023-09-04  5:05 ` [RFC PATCH v3 4/7] coresight: tmc: Enable panic sync handling Linu Cherian
2023-09-04  5:05 ` [RFC PATCH v3 5/7] coresight: tmc: Add support for reading tracedata from previous boot Linu Cherian
2023-09-04  5:05 ` [RFC PATCH v3 6/7] coresight: tmc: Stop trace capture on FlIn Linu Cherian
2023-09-04  5:05 ` [RFC PATCH v3 7/7] coresight: etm4x: Configure ETM to trigger on panic Linu Cherian
2023-09-15 13:50 ` [RFC PATCH v3 0/8] Coresight for Kernel panic and watchdog reset James Clark
2023-09-19 11:39   ` [EXT] " Linu Cherian
2023-09-19 13:10     ` James Clark
2023-09-27  3:48       ` Linu Cherian

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