From: Linu Cherian <lcherian@marvell.com>
To: <suzuki.poulose@arm.com>, <mike.leach@linaro.org>,
<james.clark@arm.com>, <leo.yan@linaro.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<coresight@lists.linaro.org>, <linux-kernel@vger.kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <devicetree@vger.kernel.org>,
<sgoutham@marvell.com>, <gcherian@marvell.com>,
Linu Cherian <lcherian@marvell.com>
Subject: [RFC PATCH v3 6/7] coresight: tmc: Stop trace capture on FlIn
Date: Mon, 4 Sep 2023 10:35:46 +0530 [thread overview]
Message-ID: <20230904050548.28047-7-lcherian@marvell.com> (raw)
In-Reply-To: <20230904050548.28047-1-lcherian@marvell.com>
Configure TMC ETR and ETF to flush and stop trace capture
on FlIn event. As a side effect, do manual flush only if
auto flush fails.
Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 ++++++++--
drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 ++++++++--
drivers/hwtracing/coresight/coresight-tmc.h | 3 +++
3 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index fd883e579141..9b4c208b6dc4 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -34,7 +34,7 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
- TMC_FFCR_TRIGON_TRIGIN,
+ TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH,
drvdata->base + TMC_FFCR);
writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
@@ -613,7 +613,13 @@ static int tmc_panic_sync_etf(struct coresight_device *csdev)
if (val != TMC_MODE_CIRCULAR_BUFFER)
goto out;
- tmc_flush_and_stop(drvdata);
+ val = readl(drvdata->base + TMC_FFSR);
+ /* Do manual flush and stop only if its not auto-stopped */
+ if (!(val & TMC_FFSR_FT_STOPPED)) {
+ dev_info(&csdev->dev,
+ "%s: Triggering manual flush\n", __func__);
+ tmc_flush_and_stop(drvdata);
+ }
/* Sync registers from hardware to metadata region */
tmc->sts = csdev_access_relaxed_read32(csa, TMC_STS);
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 7fe5d70a393a..323e503bcfa7 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1098,7 +1098,7 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
- TMC_FFCR_TRIGON_TRIGIN,
+ TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH,
drvdata->base + TMC_FFCR);
writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
tmc_enable_hw(drvdata);
@@ -1829,7 +1829,13 @@ static int tmc_panic_sync_etr(struct coresight_device *csdev)
if (!(val & TMC_CTL_CAPT_EN))
goto out;
- tmc_flush_and_stop(drvdata);
+ val = readl(drvdata->base + TMC_FFSR);
+ /* Do manual flush and stop only if its not auto-stopped */
+ if (!(val & TMC_FFSR_FT_STOPPED)) {
+ dev_info(&csdev->dev,
+ "%s: Triggering manual flush\n", __func__);
+ tmc_flush_and_stop(drvdata);
+ }
/* Sync registers from hardware to metadata region */
tmc->size = csdev_access_relaxed_read32(csa, TMC_RSZ);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index a95ba0a8ed93..b08b649f1fd4 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -76,6 +76,9 @@
#define TMC_AXICTL_AXCACHE_OS (0xf << 2)
#define TMC_AXICTL_ARCACHE_OS (0xf << 16)
+/* TMC_FFSR - 0x300 */
+#define TMC_FFSR_FT_STOPPED BIT(1)
+
/* TMC_FFCR - 0x304 */
#define TMC_FFCR_FLUSHMAN_BIT 6
#define TMC_FFCR_EN_FMT BIT(0)
--
2.41.0
next prev parent reply other threads:[~2023-09-04 5:06 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-04 5:05 [RFC PATCH v3 0/8] Coresight for Kernel panic and watchdog reset Linu Cherian
2023-09-04 5:05 ` [RFC PATCH v3 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property Linu Cherian
2023-09-04 6:23 ` Rob Herring
2023-09-09 14:12 ` [EXT] " Linu Cherian
2023-09-04 8:26 ` Suzuki K Poulose
2023-09-05 15:35 ` Rob Herring
2023-09-09 14:06 ` [EXT] " Linu Cherian
2023-09-04 5:05 ` [RFC PATCH v3 2/7] coresight: tmc-etr: Add support to use reserved trace memory Linu Cherian
2023-09-04 5:05 ` [RFC PATCH v3 3/7] coresight: core: Add provision for panic callbacks Linu Cherian
2023-09-04 5:05 ` [RFC PATCH v3 4/7] coresight: tmc: Enable panic sync handling Linu Cherian
2023-09-04 5:05 ` [RFC PATCH v3 5/7] coresight: tmc: Add support for reading tracedata from previous boot Linu Cherian
2023-09-04 5:05 ` Linu Cherian [this message]
2023-09-04 5:05 ` [RFC PATCH v3 7/7] coresight: etm4x: Configure ETM to trigger on panic Linu Cherian
2023-09-15 13:50 ` [RFC PATCH v3 0/8] Coresight for Kernel panic and watchdog reset James Clark
2023-09-19 11:39 ` [EXT] " Linu Cherian
2023-09-19 13:10 ` James Clark
2023-09-27 3:48 ` Linu Cherian
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