From: Hsiao Chien Sung <shawn.sung@mediatek.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
CK Hu <ck.hu@mediatek.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Fei Shao <fshao@chromium.org>, Sean Paul <sean@poorly.run>,
Johnson Wang <johnson.wang@mediatek.corp-partner.google.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
Moudy Ho <moudy.ho@mediatek.com>,
Hsiao Chien Sung <shawn.sung@mediatek.com>,
"Jason-JH . Lin" <jason-jh.lin@mediatek.com>,
Nathan Lu <nathan.lu@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v10 13/24] drm/mediatek: Manage component's clock with function pointers
Date: Thu, 19 Oct 2023 13:56:08 +0800 [thread overview]
Message-ID: <20231019055619.19358-14-shawn.sung@mediatek.com> (raw)
In-Reply-To: <20231019055619.19358-1-shawn.sung@mediatek.com>
By registering component related functions to the pointers,
we can easily manage them within a for-loop and simplify the
logic of clock control significantly.
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 89 +++++++++----------
1 file changed, 43 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index d55d8931a36f..81067f49ea69 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -53,6 +53,7 @@ struct ovl_adaptor_comp_match {
enum mtk_ovl_adaptor_comp_type type;
enum mtk_ddp_comp_id comp_id;
int alias_id;
+ const struct mtk_ddp_comp_funcs *funcs;
};
struct mtk_disp_ovl_adaptor {
@@ -67,20 +68,35 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
[OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
};
+static const struct mtk_ddp_comp_funcs ethdr = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs rdma = {
+ .clk_enable = mtk_mdp_rdma_clk_enable,
+ .clk_disable = mtk_mdp_rdma_clk_disable,
+};
+
static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
- [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 },
- [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 },
- [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 },
- [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 },
- [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 },
- [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
- [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
- [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
- [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
- [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
- [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
- [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 },
- [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 },
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7, &rdma },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1, &merge },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &merge },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &merge },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &merge },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, ðdr },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -196,40 +212,25 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
ret = pm_runtime_get_sync(comp);
if (ret < 0) {
dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
- goto pwr_err;
+ goto error;
}
}
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
comp = ovl_adaptor->ovl_adaptor_comp[i];
-
- if (i < OVL_ADAPTOR_MERGE0)
- ret = mtk_mdp_rdma_clk_enable(comp);
- else if (i < OVL_ADAPTOR_ETHDR0)
- ret = mtk_merge_clk_enable(comp);
- else
- ret = mtk_ethdr_clk_enable(comp);
+ if (!comp || !comp_matches[i].funcs->clk_enable)
+ continue;
+ ret = comp_matches[i].funcs->clk_enable(comp);
if (ret) {
dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret);
- goto clk_err;
+ while (--i >= 0)
+ comp_matches[i].funcs->clk_disable(comp);
+ i = OVL_ADAPTOR_MERGE0;
+ goto error;
}
}
-
- return ret;
-
-clk_err:
- while (--i >= 0) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
- if (i < OVL_ADAPTOR_MERGE0)
- mtk_mdp_rdma_clk_disable(comp);
- else if (i < OVL_ADAPTOR_ETHDR0)
- mtk_merge_clk_disable(comp);
- else
- mtk_ethdr_clk_disable(comp);
- }
- i = OVL_ADAPTOR_MERGE0;
-
-pwr_err:
+ return 0;
+error:
while (--i >= 0)
pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
@@ -244,15 +245,11 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
comp = ovl_adaptor->ovl_adaptor_comp[i];
-
- if (i < OVL_ADAPTOR_MERGE0) {
- mtk_mdp_rdma_clk_disable(comp);
+ if (!comp || !comp_matches[i].funcs->clk_disable)
+ continue;
+ comp_matches[i].funcs->clk_disable(comp);
+ if (i < OVL_ADAPTOR_MERGE0)
pm_runtime_put(comp);
- } else if (i < OVL_ADAPTOR_ETHDR0) {
- mtk_merge_clk_disable(comp);
- } else {
- mtk_ethdr_clk_disable(comp);
- }
}
}
--
2.18.0
next prev parent reply other threads:[~2023-10-19 5:58 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 5:55 [PATCH v10 00/24] Add display driver for MT8188 VDOSYS1 Hsiao Chien Sung
2023-10-19 5:55 ` [PATCH v10 01/24] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 Hsiao Chien Sung
2023-10-19 5:55 ` [PATCH v10 02/24] dt-bindings: display: mediatek: mdp-rdma: " Hsiao Chien Sung
2023-10-19 5:55 ` [PATCH v10 03/24] dt-bindings: display: mediatek: merge: " Hsiao Chien Sung
2023-10-19 5:55 ` [PATCH v10 04/24] dt-bindings: display: mediatek: padding: Add MT8188 Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 05/24] dt-bindings: arm: mediatek: Add compatible for MT8188 Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 06/24] dt-bindings: reset: mt8188: Add VDOSYS reset control bits Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 07/24] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 08/24] soc: mediatek: Support MT8188 VDOSYS1 Padding " Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 09/24] soc: mediatek: Support reset bit mapping in mmsys driver Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 10/24] soc: mediatek: Add MT8188 VDOSYS reset bit map Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 11/24] drm/mediatek: Rename OVL_ADAPTOR_TYPE_RDMA Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 12/24] drm/mediatek: Add component ID to component match structure Hsiao Chien Sung
2023-10-19 5:56 ` Hsiao Chien Sung [this message]
2023-10-19 9:10 ` [PATCH v10 13/24] drm/mediatek: Manage component's clock with function pointers AngeloGioacchino Del Regno
2023-10-24 7:55 ` CK Hu (胡俊光)
2023-10-19 5:56 ` [PATCH v10 14/24] drm/mediatek: Power on/off devices " Hsiao Chien Sung
2023-10-19 9:07 ` AngeloGioacchino Del Regno
2023-10-24 8:12 ` CK Hu (胡俊光)
2023-10-19 5:56 ` [PATCH v10 15/24] drm/mediatek: Remove ineffectual power management codes Hsiao Chien Sung
2023-10-19 9:07 ` AngeloGioacchino Del Regno
2023-10-19 9:52 ` Shawn Sung (宋孝謙)
2023-10-19 10:17 ` AngeloGioacchino Del Regno
2023-10-24 9:25 ` CK Hu (胡俊光)
2023-10-24 9:39 ` Shawn Sung (宋孝謙)
2023-10-19 5:56 ` [PATCH v10 16/24] drm/mediatek: Start/Stop components with function pointers Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 17/24] drm/mediatek: Sort OVL adaptor components Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 18/24] drm/mediatek: Refine device table of OVL adaptor Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 19/24] drm/mediatek: Support MT8188 Padding in display driver Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 20/24] drm/mediatek: Add Padding to OVL adaptor Hsiao Chien Sung
2023-10-19 9:10 ` AngeloGioacchino Del Regno
2023-10-19 9:20 ` Shawn Sung (宋孝謙)
2023-10-19 9:55 ` AngeloGioacchino Del Regno
2023-10-19 11:50 ` Shawn Sung (宋孝謙)
2023-10-19 5:56 ` [PATCH v10 21/24] drm/mediatek: Return error if MDP RDMA failed to enable the clock Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 22/24] drm/mediatek: Remove the redundant driver data for DPI Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 23/24] drm/mediatek: Fix underrun in VDO1 when switches off the layer Hsiao Chien Sung
2023-10-19 5:56 ` [PATCH v10 24/24] drm/mediatek: Support MT8188 VDOSYS1 in display driver Hsiao Chien Sung
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