From: Conor Dooley <conor.dooley@microchip.com>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: "Wang, Xiao W" <xiao.w.wang@intel.com>,
"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"ardb@kernel.org" <ardb@kernel.org>,
"anup@brainfault.org" <anup@brainfault.org>,
"Li, Haicheng" <haicheng.li@intel.com>,
"ajones@ventanamicro.com" <ajones@ventanamicro.com>,
"Liu, Yujie" <yujie.liu@intel.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-efi@vger.kernel.org" <linux-efi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 2/2] riscv: Optimize bitops with Zbb extension
Date: Tue, 31 Oct 2023 07:52:50 +0000 [thread overview]
Message-ID: <20231031-triage-glacial-d70f5951627e@wendy> (raw)
In-Reply-To: <ZUBgHC1GBm/Jg+cy@ghost>
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> > > > +static __always_inline unsigned long variable__ffs(unsigned long word)
> > > > +{
> > > > + int num;
> > > > +
> > > > + asm_volatile_goto(
> > > > + ALTERNATIVE("j %l[legacy]", "nop", 0, RISCV_ISA_EXT_ZBB, 1)
> > > > + : : : : legacy);
> > > > +
> > >
> > > On this and following asm blocks, checkpatch outputs: "Lines should not
> > > end with a '('".
> >
> > I did below check, but I got no warning.
> > # ./scripts/checkpatch.pl v4-0002-riscv-Optimize-bitops-with-Zbb-extension.patch
> > total: 0 errors, 0 warnings, 280 lines checked
> > May I know how you do the check?
> > BTW, I see arch/riscv/include/asm/jump_label.h and arch/riscv/include/asm/cpufeature.h have similar code.
>
> I normally use the --strict flag since that is what the Patchwork server
> uses.
FWIW, checkpatch output does require human interpretation. It is only a
"dumb" perl script, and particularly for asm stuff the complaints can
often be ignored. IMO, this is one of those times.
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prev parent reply other threads:[~2023-10-31 7:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-30 6:39 [PATCH v4 0/2] " Xiao Wang
2023-10-30 6:39 ` [PATCH v4 1/2] riscv: Rearrange hwcap.h and cpufeature.h Xiao Wang
2023-10-30 6:39 ` [PATCH v4 2/2] riscv: Optimize bitops with Zbb extension Xiao Wang
2023-10-30 20:36 ` Charlie Jenkins
2023-10-31 1:53 ` Wang, Xiao W
2023-10-31 2:02 ` Charlie Jenkins
2023-10-31 7:52 ` Conor Dooley [this message]
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