* [PATCH] clk: rockchip: rk3128: Fix HCLK_OTG gate register
@ 2023-10-31 11:18 Weihao Li
2023-11-17 9:50 ` Heiko Stuebner
0 siblings, 1 reply; 2+ messages in thread
From: Weihao Li @ 2023-10-31 11:18 UTC (permalink / raw)
To: mturquette, sboyd, heiko
Cc: linux-clk, linux-arm-kernel, linux-kernel, linux-rockchip, Weihao Li
The HCLK_OTG gate control is in CRU_CLKGATE5_CON, not CRU_CLKGATE3_CON.
Signed-off-by: Weihao Li <cn.liweihao@gmail.com>
---
drivers/clk/rockchip/clk-rk3128.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index aa53797dbfc1..7782785a86e6 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -490,7 +490,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
- GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 13, GFLAGS),
+ GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS),
--
2.20.1
^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [PATCH] clk: rockchip: rk3128: Fix HCLK_OTG gate register
2023-10-31 11:18 [PATCH] clk: rockchip: rk3128: Fix HCLK_OTG gate register Weihao Li
@ 2023-11-17 9:50 ` Heiko Stuebner
0 siblings, 0 replies; 2+ messages in thread
From: Heiko Stuebner @ 2023-11-17 9:50 UTC (permalink / raw)
To: mturquette, Weihao Li, sboyd
Cc: Heiko Stuebner, linux-kernel, linux-rockchip, linux-clk,
linux-arm-kernel
On Tue, 31 Oct 2023 19:18:16 +0800, Weihao Li wrote:
> The HCLK_OTG gate control is in CRU_CLKGATE5_CON, not CRU_CLKGATE3_CON.
>
>
Applied, thanks!
[1/1] clk: rockchip: rk3128: Fix HCLK_OTG gate register
commit: c6c5a5580dcb6631aa6369dabe12ef3ce784d1d2
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-10-31 11:18 [PATCH] clk: rockchip: rk3128: Fix HCLK_OTG gate register Weihao Li
2023-11-17 9:50 ` Heiko Stuebner
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