From: Samuel Holland <samuel.holland@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Samuel Holland <samuel.holland@sifive.com>
Subject: [PATCH v3 3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
Date: Tue, 21 Nov 2023 17:07:14 -0800 [thread overview]
Message-ID: <20231122010815.3545294-4-samuel.holland@sifive.com> (raw)
In-Reply-To: <20231122010815.3545294-1-samuel.holland@sifive.com>
Since implementations affected by SiFive errata CIP-1200 always use the
global variant of the sfence.vma instruction, they only need to execute
the instruction once. The range-based loop only hurts performance.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
Changes in v3:
- New patch for v3
arch/riscv/errata/sifive/errata.c | 3 +++
arch/riscv/include/asm/tlbflush.h | 2 ++
arch/riscv/mm/tlbflush.c | 2 +-
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c
index 3d9a32d791f7..00e011d78866 100644
--- a/arch/riscv/errata/sifive/errata.c
+++ b/arch/riscv/errata/sifive/errata.c
@@ -42,6 +42,9 @@ static bool errata_cip_1200_check_func(unsigned long arch_id, unsigned long imp
return false;
if ((impid & 0xffffff) > 0x200630 || impid == 0x1200626)
return false;
+
+ tlb_flush_all_threshold = 0;
+
return true;
}
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index e529a643be17..3b393f765805 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -62,6 +62,8 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end);
void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
#endif
+
+extern unsigned long tlb_flush_all_threshold;
#else /* CONFIG_MMU */
#define local_flush_tlb_all() do { } while (0)
#endif /* CONFIG_MMU */
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 0feccb8932d2..27b3744b5673 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -11,7 +11,7 @@
* Flush entire TLB if number of entries to be flushed is greater
* than the threshold below.
*/
-static unsigned long tlb_flush_all_threshold __read_mostly = 64;
+unsigned long tlb_flush_all_threshold __read_mostly = 64;
static void local_flush_tlb_range_threshold_asid(unsigned long start,
unsigned long size,
--
2.42.0
next prev parent reply other threads:[~2023-11-22 1:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-22 1:07 [PATCH v3 0/8] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2023-11-22 1:07 ` [PATCH v3 1/8] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2023-11-22 1:07 ` [PATCH v3 2/8] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2023-11-22 1:07 ` Samuel Holland [this message]
2023-11-22 17:34 ` [PATCH v3 3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 kernel test robot
2023-11-22 1:07 ` [PATCH v3 4/8] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2023-11-22 1:07 ` [PATCH v3 5/8] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2023-11-22 1:07 ` [PATCH v3 6/8] riscv: mm: Make asid_bits a local variable Samuel Holland
2023-11-22 1:07 ` [PATCH v3 7/8] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2023-11-22 1:07 ` [PATCH v3 8/8] riscv: mm: Always use ASID to flush MM contexts Samuel Holland
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