Re: [PATCH 2/4] clk: sophgo: Add CV1800 series clock controller driver

[kernel test robot <lkp@intel.com>]

Hi Inochi,

kernel test robot noticed the following build warnings:

[auto build test WARNING on next-20231205]
[also build test WARNING on linus/master v6.7-rc4]
[cannot apply to clk/clk-next robh/for-next v6.7-rc4 v6.7-rc3 v6.7-rc2]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Inochi-Amaoto/dt-bindings-clock-sophgo-Add-CV1800-bindings/20231205-174631
base:   next-20231205
patch link:    https://lore.kernel.org/r/IA1PR20MB4953946E2F8D8795DC261DBFBB85A%40IA1PR20MB4953.namprd20.prod.outlook.com
patch subject: [PATCH 2/4] clk: sophgo: Add CV1800 series clock controller driver
config: i386-buildonly-randconfig-003-20231206 (https://download.01.org/0day-ci/archive/20231206/202312062352.3dWKz9Hm-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231206/202312062352.3dWKz9Hm-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312062352.3dWKz9Hm-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/clk/sophgo/clk-cv18xx-ip.c:347: warning: Function parameter or member 'hw' not described in 'bypass_div_get_parent'
>> drivers/clk/sophgo/clk-cv18xx-ip.c:347: warning: expecting prototype for clokc parent list(). Prototype was for bypass_div_get_parent() instead


vim +347 drivers/clk/sophgo/clk-cv18xx-ip.c

   341	
   342	/**
   343	 * clokc parent list:
   344	 * | osc | div0 | div1 | div2 | div3 |
   345	 */
   346	static u8 bypass_div_get_parent(struct clk_hw *hw)
 > 347	{
   348		struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
   349	
   350		if (cv1800_clk_checkbit(&div->div.common, &div->bypass))
   351			return 0;
   352	
   353		return 1;
   354	}
   355	

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