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From: Sean Christopherson <seanjc@google.com>
To: Sean Christopherson <seanjc@google.com>,
	Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Sandipan Das <sandipan.das@amd.com>,
	Jim Mattson <jmattson@google.com>,
	 Like Xu <like.xu.linux@gmail.com>
Subject: [PATCH 05/10] KVM: x86: Inhibit code #DBs in MOV-SS shadow for all Intel compat vCPUs
Date: Fri,  5 Apr 2024 16:55:58 -0700	[thread overview]
Message-ID: <20240405235603.1173076-6-seanjc@google.com> (raw)
In-Reply-To: <20240405235603.1173076-1-seanjc@google.com>

Treat code #DBs as inhibited in MOV/POP-SS shadows for vCPU models that
are Intel compatible, not just strictly vCPUs with vendor==Intel.  The
behavior is explicitly called out in the SDM, and thus architectural, i.e.
applies to all CPUs that implement Intel's architecture, and isn't a quirk
that is unique to CPUs manufactured by Intel:

  However, if an instruction breakpoint is placed on an instruction located
  immediately after a POP SS/MOV SS instruction, the breakpoint will be
  suppressed as if EFLAGS.RF were 1.

Applying the behavior strictly to Intel wasn't intentional, KVM simply
didn't have a concept of "Intel compatible" as of commit baf67ca8e545
("KVM: x86: Suppress code #DBs on Intel if MOV/POP SS blocking is active").

Signed-off-by: Sean Christopherson <seanjc@google.com>
---
 arch/x86/kvm/x86.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index d9719141502a..8ea6f4fc910f 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -8984,19 +8984,17 @@ EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
 
 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
 {
-	u32 shadow;
-
 	if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
 		return true;
 
 	/*
-	 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
-	 * but AMD CPUs do not.  MOV/POP SS blocking is rare, check that first
-	 * to avoid the relatively expensive CPUID lookup.
+	 * Intel compatible CPUs inhibit code #DBs when MOV/POP SS blocking is
+	 * active, but AMD compatible CPUs do not.
 	 */
-	shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
-	return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
-	       guest_cpuid_is_intel(vcpu);
+	if (!guest_cpuid_is_intel_compatible(vcpu))
+		return false;
+
+	return static_call(kvm_x86_get_interrupt_shadow)(vcpu) & KVM_X86_SHADOW_INT_MOV_SS;
 }
 
 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
-- 
2.44.0.478.gd926399ef9-goog


  parent reply	other threads:[~2024-04-05 23:56 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-05 23:55 [PATCH 00/10] KVM: x86: Fix LVTPC masking on AMD CPUs Sean Christopherson
2024-04-05 23:55 ` [PATCH 01/10] KVM: x86: Snapshot if a vCPU's vendor model is AMD vs. Intel compatible Sean Christopherson
2024-04-05 23:55 ` [PATCH 02/10] KVM: x86/pmu: Do not mask LVTPC when handling a PMI on AMD platforms Sean Christopherson
2024-04-05 23:55 ` [PATCH 03/10] KVM: x86/pmu: Squash period for checkpointed events based on host HLE/RTM Sean Christopherson
2024-04-05 23:55 ` [PATCH 04/10] KVM: x86: Apply Intel's TSC_AUX reserved-bit behavior to Intel compat vCPUs Sean Christopherson
2024-04-05 23:55 ` Sean Christopherson [this message]
2024-04-05 23:55 ` [PATCH 06/10] KVM: x86: Use "is Intel compatible" helper to emulate SYSCALL in !64-bit Sean Christopherson
2024-04-05 23:56 ` [PATCH 07/10] KVM: SVM: Emulate SYSENTER RIP/RSP behavior for all Intel compat vCPUs Sean Christopherson
2024-04-05 23:56 ` [PATCH 08/10] KVM: x86: Allow SYSENTER in Compatibility Mode " Sean Christopherson
2024-04-05 23:56 ` [PATCH 09/10] KVM: x86: Open code vendor_intel() in string_registers_quirk() Sean Christopherson
2024-04-05 23:56 ` [PATCH 10/10] KVM: x86: Bury guest_cpuid_is_amd_or_hygon() in cpuid.c Sean Christopherson
2024-04-09  2:01 ` [PATCH 00/10] KVM: x86: Fix LVTPC masking on AMD CPUs Sean Christopherson
2024-04-11 17:03 ` Paolo Bonzini
2024-06-12  1:18 ` Sean Christopherson

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