From: Hsiao Chien Sung via B4 Relay <devnull+shawn.sung.mediatek.com@kernel.org>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
CK Hu <ck.hu@mediatek.com>,
Bibby Hsieh <bibby.hsieh@mediatek.com>,
Daniel Kurtz <djkurtz@chromium.org>,
YT Shen <yt.shen@mediatek.com>,
Mao Huang <littlecvr@chromium.org>,
"Nancy.Lin" <nancy.lin@mediatek.com>
Cc: dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Hsiao Chien Sung <shawn.sung@mediatek.com>
Subject: [PATCH v2 03/14] drm/mediatek: Fix XRGB setting error in OVL
Date: Wed, 19 Jun 2024 22:30:44 +0800 [thread overview]
Message-ID: <20240619-mediatek-drm-next-v2-3-abf68f46f8d2@mediatek.com> (raw)
In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com>
From: Hsiao Chien Sung <shawn.sung@mediatek.com>
CONST_BLD must be enabled for XRGB formats although the alpha channel
can be ignored, or OVL will still read the value from memory.
This error only affects CRC generation.
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index b552a02d7eae..bd00e5e85deb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -38,6 +38,7 @@
#define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n))
#define OVL_PITCH_MSB_2ND_SUBBUF BIT(16)
#define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
+#define OVL_CONST_BLEND BIT(28)
#define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
#define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
#define DISP_REG_OVL_ADDR_MT2701 0x0040
@@ -407,6 +408,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
unsigned int fmt = pending->format;
unsigned int offset = (pending->y << 16) | pending->x;
unsigned int src_size = (pending->height << 16) | pending->width;
+ unsigned int ignore_pixel_alpha = 0;
unsigned int con;
bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
union overlay_pitch {
@@ -428,6 +430,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
if (state->base.fb && state->base.fb->format->has_alpha)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
+ /* CONST_BLD must be enabled for XRGB formats although the alpha channel
+ * can be ignored, or OVL will still read the value from memory.
+ * For RGB888 related formats, whether CONST_BLD is enabled or not won't
+ * affect the result. Therefore we use !has_alpha as the condition.
+ */
+ if (state->base.fb && !state->base.fb->format->has_alpha)
+ ignore_pixel_alpha = OVL_CONST_BLEND;
+
if (pending->rotation & DRM_MODE_REFLECT_Y) {
con |= OVL_CON_VIRT_FLIP;
addr += (pending->height - 1) * pending->pitch;
@@ -443,8 +453,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_CON(idx));
- mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
- DISP_REG_OVL_PITCH(idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_SRC_SIZE(idx));
mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
--
Git-146)
next prev parent reply other threads:[~2024-06-19 14:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-19 14:30 [PATCH v2 00/14] Fix the errors of MediaTek display driver found by IGT Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 01/14] drm/mediatek: Add missing plane settings when async update Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 02/14] drm/mediatek: Disable 9-bit alpha in ETHDR Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` Hsiao Chien Sung via B4 Relay [this message]
2024-06-19 14:30 ` [PATCH v2 04/14] drm/mediatek: Fix XRGB setting error in Mixer Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 05/14] drm/mediatek: Turn off the layers with zero width or height Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 06/14] drm/mediatek: Add OVL compatible name for MT8195 Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 07/14] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 08/14] drm/mediatek: Add new color format MACROs in OVL Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 09/14] drm/mediatek: Set DRM mode configs accordingly Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 10/14] drm/mediatek: Support more 10bit formats in OVL Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 11/14] drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195 Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 12/14] drm/mediatek: Support DRM plane alpha in OVL Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 13/14] drm/mediatek: Support DRM plane alpha in Mixer Hsiao Chien Sung via B4 Relay
2024-06-19 14:30 ` [PATCH v2 14/14] drm/mediatek: Fix XRGB setting error in OVL Hsiao Chien Sung via B4 Relay
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