* [PATCH 1/5] arm64: dts: layerscape: add msi-cell = <1> for gic its
@ 2024-07-03 20:58 Frank Li
2024-07-03 20:58 ` [PATCH 2/5] arm64: dts: layerscape: remove big-endian for mmc nodes Frank Li
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Frank Li @ 2024-07-03 20:58 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
moderated list:ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Cc: imx
Add msi-cell = <1> for GIC ITS. msi-parent have to be kept because it is
checked by U-Boot due to historical reasons to fix up msi-map.
Fix below CHECK_DTBS warning:
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb: interrupt-controller@6000000: msi-controller@6020000: '#msi-cells' is a required property
from schema $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 7 ++++---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 9 +++++----
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 11 ++++++-----
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 15 ++++++++-------
4 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 6b6e3ee950e53..d3f69163ecd55 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -150,6 +150,7 @@ gic: interrupt-controller@6000000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
+ #msi-cells = <1>;
reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
};
};
@@ -662,7 +663,7 @@ pcie1: pcie@3400000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
@@ -701,7 +702,7 @@ pcie2: pcie@3500000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
@@ -1080,7 +1081,7 @@ pcie@1f0000000 { /* Integrated Endpoint Root Complex */
reg = <0x01 0xf0000000 0x0 0x100000>;
#address-cells = <3>;
#size-cells = <2>;
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
device_type = "pci";
bus-range = <0x0 0x0>;
dma-coherent;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 8ce4b6aae79d4..c9459e251e59c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -126,6 +126,7 @@ gic: interrupt-controller@6000000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
+ #msi-cells = <1>;
reg = <0x0 0x6020000 0 0x20000>;
};
};
@@ -575,7 +576,7 @@ pcie1: pcie@3400000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
@@ -614,7 +615,7 @@ pcie2: pcie@3500000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
@@ -652,7 +653,7 @@ pcie3: pcie@3600000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
@@ -964,7 +965,7 @@ fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
dma-coherent;
#address-cells = <3>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index bde89de2576e1..8a6c883379c26 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -63,6 +63,7 @@ gic: interrupt-controller@6000000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
+ #msi-cells = <1>;
reg = <0x0 0x6020000 0 0x20000>;
};
};
@@ -758,7 +759,7 @@ fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
dma-coherent;
#address-cells = <3>;
@@ -1085,7 +1086,7 @@ pcie1: pcie@3400000 {
dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
@@ -1107,7 +1108,7 @@ pcie2: pcie@3500000 {
dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
@@ -1129,7 +1130,7 @@ pcie3: pcie@3600000 {
dma-coherent;
num-viewport = <256>;
bus-range = <0x0 0xff>;
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
@@ -1151,7 +1152,7 @@ pcie4: pcie@3700000 {
dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 26c7ca31e22e7..e7f730d7a72e6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -398,6 +398,7 @@ gic: interrupt-controller@6000000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
+ #msi-cells = <1>;
reg = <0x0 0x6020000 0 0x20000>;
};
};
@@ -1181,7 +1182,7 @@ pcie1: pcie@3400000 {
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
@@ -1209,7 +1210,7 @@ pcie2: pcie@3500000 {
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
@@ -1237,7 +1238,7 @@ pcie3: pcie@3600000 {
ppio-wins = <24>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
@@ -1265,7 +1266,7 @@ pcie4: pcie@3700000 {
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
@@ -1293,7 +1294,7 @@ pcie5: pcie@3800000 {
ppio-wins = <24>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
@@ -1321,7 +1322,7 @@ pcie6: pcie@3900000 {
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -1777,7 +1778,7 @@ fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,
<0x00000000 0x08340000 0 0x40000>;
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
/* iommu-map property is fixed up by u-boot */
iommu-map = <0 &smmu 0 0>;
dma-coherent;
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/5] arm64: dts: layerscape: remove big-endian for mmc nodes
2024-07-03 20:58 [PATCH 1/5] arm64: dts: layerscape: add msi-cell = <1> for gic its Frank Li
@ 2024-07-03 20:58 ` Frank Li
2024-07-03 20:58 ` [PATCH 3/5] arm64: dts: fsl-ls1046a: remove big-endian at memory-controller Frank Li
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Frank Li @ 2024-07-03 20:58 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
moderated list:ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Cc: imx
According to binding doc fsl,esdhc.yaml, the default endian mode is
big-endian. So remove big-endian property to fix below CHECK_DTBS warnings:
arm64/boot/dts/freescale/fsl-ls1012a-qds.dtb: mmc@1560000: Unevaluated properties are not allowed ('big-endian' was unexpected)
from schema $id: http://devicetree.org/schemas/mmc/fsl,esdhc.yaml
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 --
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 -
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 --
3 files changed, 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index e61ea7e0737e4..42d2134b8170b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -164,7 +164,6 @@ esdhc0: mmc@1560000 {
QORIQ_CLK_PLL_DIV(1)>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
- big-endian;
bus-width = <4>;
status = "disabled";
};
@@ -183,7 +182,6 @@ esdhc1: mmc@1580000 {
QORIQ_CLK_PLL_DIV(1)>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
- big-endian;
broken-cd;
bus-width = <4>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 17f4e31711209..9a19bcd1850d9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -431,7 +431,6 @@ esdhc: mmc@1560000 {
clock-frequency = <0>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
- big-endian;
bus-width = <4>;
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 200e52622f998..9bbe2d686a39f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -315,7 +315,6 @@ esdhc: mmc@1560000 {
clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
- big-endian;
bus-width = <4>;
};
@@ -694,7 +693,6 @@ wdog0: watchdog@2ad0000 {
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
- big-endian;
};
edma0: dma-controller@2c00000 {
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/5] arm64: dts: fsl-ls1046a: remove big-endian at memory-controller
2024-07-03 20:58 [PATCH 1/5] arm64: dts: layerscape: add msi-cell = <1> for gic its Frank Li
2024-07-03 20:58 ` [PATCH 2/5] arm64: dts: layerscape: remove big-endian for mmc nodes Frank Li
@ 2024-07-03 20:58 ` Frank Li
2024-07-03 20:58 ` [PATCH 4/5] arm64: dts: layersacpe: remove undocumented fsl,ls-pcie-ep Frank Li
2024-07-03 20:58 ` [PATCH 5/5] arm64: dts: fsl,ls2085a: remove fsl,ls2085a-pcie Frank Li
3 siblings, 0 replies; 6+ messages in thread
From: Frank Li @ 2024-07-03 20:58 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
moderated list:ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Cc: imx
According to binding doc fsl,ddr.yaml, big-endian is default setting. So
remove it to fix below CHECK_DTBS warnings.
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: memory-controller@1080000: 'big-endian' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 -
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 9a19bcd1850d9..3dcfa50cedf9a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -438,7 +438,6 @@ ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
};
tmu: tmu@1f00000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 9bbe2d686a39f..1ae73708bdc60 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -282,7 +282,6 @@ ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
};
ifc: memory-controller@1530000 {
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/5] arm64: dts: layersacpe: remove undocumented fsl,ls-pcie-ep
2024-07-03 20:58 [PATCH 1/5] arm64: dts: layerscape: add msi-cell = <1> for gic its Frank Li
2024-07-03 20:58 ` [PATCH 2/5] arm64: dts: layerscape: remove big-endian for mmc nodes Frank Li
2024-07-03 20:58 ` [PATCH 3/5] arm64: dts: fsl-ls1046a: remove big-endian at memory-controller Frank Li
@ 2024-07-03 20:58 ` Frank Li
2024-07-03 22:18 ` Frank Li
2024-07-03 20:58 ` [PATCH 5/5] arm64: dts: fsl,ls2085a: remove fsl,ls2085a-pcie Frank Li
3 siblings, 1 reply; 6+ messages in thread
From: Frank Li @ 2024-07-03 20:58 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
moderated list:ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Cc: imx
Remove undocumented compatible string fsl,ls-pcie-ep to fix below
CHECK_DTBS warning.
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dtb: pcie_ep@3400000: compatible: ['fsl,ls1046a-pcie-ep', 'fsl,ls-pcie-ep'] is too long
from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 +++---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 1ae73708bdc60..c77613e98e539 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -820,7 +820,7 @@ pcie1: pcie@3400000 {
};
pcie_ep1: pcie_ep@3400000 {
- compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
+ compatible = "fsl,ls1046a-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000>,
<0x40 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
@@ -859,7 +859,7 @@ pcie2: pcie@3500000 {
};
pcie_ep2: pcie_ep@3500000 {
- compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
+ compatible = "fsl,ls1046a-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000>,
<0x48 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
@@ -898,7 +898,7 @@ pcie3: pcie@3600000 {
};
pcie_ep3: pcie_ep@3600000 {
- compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
+ compatible = "fsl,ls1046a-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000>,
<0x50 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index c9459e251e59c..c453b59598f17 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -588,7 +588,7 @@ pcie1: pcie@3400000 {
};
pcie_ep1: pcie-ep@3400000 {
- compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
+ compatible = "fsl,ls1088a-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000>,
<0x20 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
@@ -627,7 +627,7 @@ pcie2: pcie@3500000 {
};
pcie_ep2: pcie-ep@3500000 {
- compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
+ compatible = "fsl,ls1088a-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000>,
<0x28 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
@@ -665,7 +665,7 @@ pcie3: pcie@3600000 {
};
pcie_ep3: pcie-ep@3600000 {
- compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
+ compatible = "fsl,ls1088a-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000>,
<0x30 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 5/5] arm64: dts: fsl,ls2085a: remove fsl,ls2085a-pcie
2024-07-03 20:58 [PATCH 1/5] arm64: dts: layerscape: add msi-cell = <1> for gic its Frank Li
` (2 preceding siblings ...)
2024-07-03 20:58 ` [PATCH 4/5] arm64: dts: layersacpe: remove undocumented fsl,ls-pcie-ep Frank Li
@ 2024-07-03 20:58 ` Frank Li
3 siblings, 0 replies; 6+ messages in thread
From: Frank Li @ 2024-07-03 20:58 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
moderated list:ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Cc: imx
fsl,ls2080a-pcie actual is the same as fsl,ls2085a-pcie. Only keep one is
enough, so remove "fsl,ls2085a-pcie" to fix below warnings.
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dtb: pcie@3400000: compatible: ['fsl,ls2080a-pcie', 'fsl,ls2085a-pcie'] is too long
from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 8a6c883379c26..679891eef939b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -1076,7 +1076,7 @@ QORIQ_CLK_PLL_DIV(4)>,
};
pcie1: pcie@3400000 {
- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
+ compatible = "fsl,ls2080a-pcie";
reg-names = "regs", "config";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@@ -1098,7 +1098,7 @@ pcie1: pcie@3400000 {
};
pcie2: pcie@3500000 {
- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
+ compatible = "fsl,ls2080a-pcie";
reg-names = "regs", "config";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@@ -1120,7 +1120,7 @@ pcie2: pcie@3500000 {
};
pcie3: pcie@3600000 {
- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
+ compatible = "fsl,ls2080a-pcie";
reg-names = "regs", "config";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@@ -1142,7 +1142,7 @@ pcie3: pcie@3600000 {
};
pcie4: pcie@3700000 {
- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
+ compatible = "fsl,ls2080a-pcie";
reg-names = "regs", "config";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 4/5] arm64: dts: layersacpe: remove undocumented fsl,ls-pcie-ep
2024-07-03 20:58 ` [PATCH 4/5] arm64: dts: layersacpe: remove undocumented fsl,ls-pcie-ep Frank Li
@ 2024-07-03 22:18 ` Frank Li
0 siblings, 0 replies; 6+ messages in thread
From: Frank Li @ 2024-07-03 22:18 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
moderated list:ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Cc: imx
sorry, miss spell 'layersacpe', will fix soon.
On Wed, Jul 03, 2024 at 04:58:46PM -0400, Frank Li wrote:
> Remove undocumented compatible string fsl,ls-pcie-ep to fix below
> CHECK_DTBS warning.
> arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dtb: pcie_ep@3400000: compatible: ['fsl,ls1046a-pcie-ep', 'fsl,ls-pcie-ep'] is too long
> from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 +++---
> arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index 1ae73708bdc60..c77613e98e539 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -820,7 +820,7 @@ pcie1: pcie@3400000 {
> };
>
> pcie_ep1: pcie_ep@3400000 {
> - compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
> + compatible = "fsl,ls1046a-pcie-ep";
> reg = <0x00 0x03400000 0x0 0x00100000>,
> <0x40 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> @@ -859,7 +859,7 @@ pcie2: pcie@3500000 {
> };
>
> pcie_ep2: pcie_ep@3500000 {
> - compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
> + compatible = "fsl,ls1046a-pcie-ep";
> reg = <0x00 0x03500000 0x0 0x00100000>,
> <0x48 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> @@ -898,7 +898,7 @@ pcie3: pcie@3600000 {
> };
>
> pcie_ep3: pcie_ep@3600000 {
> - compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
> + compatible = "fsl,ls1046a-pcie-ep";
> reg = <0x00 0x03600000 0x0 0x00100000>,
> <0x50 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index c9459e251e59c..c453b59598f17 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -588,7 +588,7 @@ pcie1: pcie@3400000 {
> };
>
> pcie_ep1: pcie-ep@3400000 {
> - compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
> + compatible = "fsl,ls1088a-pcie-ep";
> reg = <0x00 0x03400000 0x0 0x00100000>,
> <0x20 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> @@ -627,7 +627,7 @@ pcie2: pcie@3500000 {
> };
>
> pcie_ep2: pcie-ep@3500000 {
> - compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
> + compatible = "fsl,ls1088a-pcie-ep";
> reg = <0x00 0x03500000 0x0 0x00100000>,
> <0x28 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> @@ -665,7 +665,7 @@ pcie3: pcie@3600000 {
> };
>
> pcie_ep3: pcie-ep@3600000 {
> - compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
> + compatible = "fsl,ls1088a-pcie-ep";
> reg = <0x00 0x03600000 0x0 0x00100000>,
> <0x30 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-07-03 22:18 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-07-03 20:58 [PATCH 1/5] arm64: dts: layerscape: add msi-cell = <1> for gic its Frank Li
2024-07-03 20:58 ` [PATCH 2/5] arm64: dts: layerscape: remove big-endian for mmc nodes Frank Li
2024-07-03 20:58 ` [PATCH 3/5] arm64: dts: fsl-ls1046a: remove big-endian at memory-controller Frank Li
2024-07-03 20:58 ` [PATCH 4/5] arm64: dts: layersacpe: remove undocumented fsl,ls-pcie-ep Frank Li
2024-07-03 22:18 ` Frank Li
2024-07-03 20:58 ` [PATCH 5/5] arm64: dts: fsl,ls2085a: remove fsl,ls2085a-pcie Frank Li
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