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From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org,
	Nicolas Saenz Julienne <nsaenz@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Cyril Brulebois <kibi@debian.org>,
	Stanimir Varbanov <svarbanov@suse.de>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
	james.quinlan@broadcom.com
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v3 12/12] PCI: brcmstb: Enable 7712 SOCs
Date: Wed, 10 Jul 2024 18:16:26 -0400	[thread overview]
Message-ID: <20240710221630.29561-13-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20240710221630.29561-1-james.quinlan@broadcom.com>

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The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712).

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
---
 drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index b6b21e0a56a8..3bc6b49227fe 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1192,6 +1192,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
 	const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
 	u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
 
+	/* 7712 does not have this (RGR1) timer */
+	if (pcie->model == BCM7712)
+		return;
+
 	/* Each unit in timeout register is 1/216,000,000 seconds */
 	writel(216 * timeout_us, pcie->base + REG_OFFSET);
 }
@@ -1663,6 +1667,13 @@ static const int pcie_offsets_bmips_7425[] = {
 	[PCIE_INTR2_CPU_BASE] = 0x4300,
 };
 
+static const int pcie_offset_bcm7712[] = {
+	[EXT_CFG_INDEX]  = 0x9000,
+	[EXT_CFG_DATA]   = 0x9004,
+	[PCIE_HARD_DEBUG] = 0x4304,
+	[PCIE_INTR2_CPU_BASE] = 0x4400,
+};
+
 static const struct pcie_cfg_data generic_cfg = {
 	.offsets	= pcie_offsets,
 	.model		= GENERIC,
@@ -1728,6 +1739,14 @@ static const struct pcie_cfg_data bcm7216_cfg = {
 	.num_inbound	= 3,
 };
 
+static const struct pcie_cfg_data bcm7712_cfg = {
+	.offsets	= pcie_offset_bcm7712,
+	.perst_set	= brcm_pcie_perst_set_7278,
+	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+	.model		= BCM7712,
+	.num_inbound	= 10,
+};
+
 static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
 	{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
@@ -1737,6 +1756,7 @@ static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
 	{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
 	{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
+	{ .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
 	{},
 };
 
-- 
2.17.1


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  parent reply	other threads:[~2024-07-10 22:16 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-10 22:16 [PATCH v3 00/12] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-07-10 22:16 ` [PATCH v3 01/12] dt-bindings: PCI: Change brcmstb YAML maintainer Jim Quinlan
2024-07-11 21:24   ` Rob Herring (Arm)
2024-07-14 20:18   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 02/12] dt-bindings: PCI: Cleanup of brcmstb YAML and add 7712 SoC Jim Quinlan
2024-07-11  6:21   ` Krzysztof Kozlowski
2024-07-10 22:16 ` [PATCH v3 03/12] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-07-15 10:32   ` Stanimir Varbanov
2024-07-15 21:10   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 04/12] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-07-13 19:12   ` Amit Singh Tomar
2024-07-16 18:40     ` Jim Quinlan
2024-07-16 19:06       ` Amit Singh Tomar
2024-07-15 10:33   ` Stanimir Varbanov
2024-07-15 21:10   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 05/12] PCI: brcmstb: Use swinit " Jim Quinlan
2024-07-15 10:35   ` Stanimir Varbanov
2024-07-15 21:09   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-07-15 10:36   ` Stanimir Varbanov
2024-07-15 21:09   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 07/12] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-07-15 21:08   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-07-15 21:08   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 09/12] PCI: brcmstb: Refactor for chips with many regular inbound BARs Jim Quinlan
2024-07-15 10:38   ` Stanimir Varbanov
2024-07-10 22:16 ` [PATCH v3 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-07-15 14:01   ` Stanimir Varbanov
2024-07-15 21:08   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 11/12] PCI: brcmstb: Change field name from 'type' to 'model' Jim Quinlan
2024-07-15 21:06   ` Florian Fainelli
2024-07-10 22:16 ` Jim Quinlan [this message]
2024-07-15 21:12   ` [PATCH v3 12/12] PCI: brcmstb: Enable 7712 SOCs Florian Fainelli
2024-07-14 20:15 ` [PATCH v3 00/12] PCI: brcnstb: Enable STB 7712 SOC Florian Fainelli
2024-07-15 17:24 ` Florian Fainelli

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