From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: Huacai Chen <chenhuacai@kernel.org>,
WANG Xuerui <kernel@xen0n.name>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-mips@vger.kernel.org,
kvm@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH 1/5] LoongArch: Rename cpu_has_csr as cpu_has_iocsr
Date: Sat, 07 Sep 2024 11:17:03 +0100 [thread overview]
Message-ID: <20240907-iocsr-v1-1-0c99b3334444@flygoat.com> (raw)
In-Reply-To: <20240907-iocsr-v1-0-0c99b3334444@flygoat.com>
It meant to be IOCSR as CSR is not optional for LoongArch.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/loongarch/include/asm/cpu-features.h | 2 +-
arch/loongarch/include/asm/cpu.h | 2 +-
arch/loongarch/kernel/cpu-probe.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/include/asm/cpu-features.h
index 16a716f88a5c..0190ed28a647 100644
--- a/arch/loongarch/include/asm/cpu-features.h
+++ b/arch/loongarch/include/asm/cpu-features.h
@@ -50,7 +50,7 @@
#define cpu_has_lbt_arm cpu_opt(LOONGARCH_CPU_LBT_ARM)
#define cpu_has_lbt_mips cpu_opt(LOONGARCH_CPU_LBT_MIPS)
#define cpu_has_lbt (cpu_has_lbt_x86|cpu_has_lbt_arm|cpu_has_lbt_mips)
-#define cpu_has_csr cpu_opt(LOONGARCH_CPU_CSR)
+#define cpu_has_iocsr cpu_opt(LOONGARCH_CPU_IOCSR)
#define cpu_has_tlb cpu_opt(LOONGARCH_CPU_TLB)
#define cpu_has_watch cpu_opt(LOONGARCH_CPU_WATCH)
#define cpu_has_vint cpu_opt(LOONGARCH_CPU_VINT)
diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h
index 843f9c4ec980..7c44f4ede3a2 100644
--- a/arch/loongarch/include/asm/cpu.h
+++ b/arch/loongarch/include/asm/cpu.h
@@ -115,7 +115,7 @@ enum cpu_type_enum {
#define LOONGARCH_CPU_LBT_ARM BIT_ULL(CPU_FEATURE_LBT_ARM)
#define LOONGARCH_CPU_LBT_MIPS BIT_ULL(CPU_FEATURE_LBT_MIPS)
#define LOONGARCH_CPU_TLB BIT_ULL(CPU_FEATURE_TLB)
-#define LOONGARCH_CPU_CSR BIT_ULL(CPU_FEATURE_CSR)
+#define LOONGARCH_CPU_IOCSR BIT_ULL(CPU_FEATURE_IOCSR)
#define LOONGARCH_CPU_WATCH BIT_ULL(CPU_FEATURE_WATCH)
#define LOONGARCH_CPU_VINT BIT_ULL(CPU_FEATURE_VINT)
#define LOONGARCH_CPU_CSRIPI BIT_ULL(CPU_FEATURE_CSRIPI)
diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
index 14f0449f5452..4446616d497c 100644
--- a/arch/loongarch/kernel/cpu-probe.c
+++ b/arch/loongarch/kernel/cpu-probe.c
@@ -91,7 +91,7 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
unsigned int config;
unsigned long asid_mask;
- c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR |
+ c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_IOCSR |
LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH;
elf_hwcap = HWCAP_LOONGARCH_CPUCFG;
--
2.46.0
next prev parent reply other threads:[~2024-09-07 10:17 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-07 10:17 [PATCH 0/5] LoongArch, MIPS: Unify Loongson IOCSR handling Jiaxun Yang
2024-09-07 10:17 ` Jiaxun Yang [this message]
2024-09-08 2:38 ` [PATCH 1/5] LoongArch: Rename cpu_has_csr as cpu_has_iocsr Huacai Chen
2024-09-07 10:17 ` [PATCH 2/5] LoongArch: Probe more CPU features from CPUCFG Jiaxun Yang
2024-09-08 2:40 ` Huacai Chen
2024-09-07 10:17 ` [PATCH 3/5] LoongArch: cpu-probe: Move IOCSR probing out of cpu_probe_common Jiaxun Yang
2024-09-08 2:47 ` Huacai Chen
2024-09-08 10:00 ` Jiaxun Yang
2024-09-07 10:17 ` [PATCH 4/5] LoongArch: Extract IOCSR definitions to standalone header Jiaxun Yang
2024-09-08 16:56 ` kernel test robot
2024-09-07 10:17 ` [PATCH 5/5] MIPS: Loongson64: Use shared IOCSR header Jiaxun Yang
2024-09-07 10:25 ` [PATCH 0/5] LoongArch, MIPS: Unify Loongson IOCSR handling Huacai Chen
2024-09-07 10:30 ` Jiaxun Yang
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