mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: Huacai Chen <chenhuacai@kernel.org>,
	WANG Xuerui <kernel@xen0n.name>,
	 "Rafael J. Wysocki" <rafael@kernel.org>,
	 Viresh Kumar <viresh.kumar@linaro.org>,
	 Thomas Gleixner <tglx@linutronix.de>,
	 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org,
	 linux-pm@vger.kernel.org, linux-mips@vger.kernel.org,
	kvm@vger.kernel.org,  Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH 2/5] LoongArch: Probe more CPU features from CPUCFG
Date: Sat, 07 Sep 2024 11:17:04 +0100	[thread overview]
Message-ID: <20240907-iocsr-v1-2-0c99b3334444@flygoat.com> (raw)
In-Reply-To: <20240907-iocsr-v1-0-0c99b3334444@flygoat.com>

Probe ISA level, TLB, IOCSR information from CPUCFG to
improve kernel resilience to different core implementations.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/loongarch/include/asm/cpu.h  |  2 +-
 arch/loongarch/kernel/cpu-probe.c | 47 ++++++++++++++++++++++++++-------------
 2 files changed, 32 insertions(+), 17 deletions(-)

diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h
index 7c44f4ede3a2..31a2de821236 100644
--- a/arch/loongarch/include/asm/cpu.h
+++ b/arch/loongarch/include/asm/cpu.h
@@ -86,7 +86,7 @@ enum cpu_type_enum {
 #define CPU_FEATURE_LBT_ARM		11	/* CPU has ARM Binary Translation */
 #define CPU_FEATURE_LBT_MIPS		12	/* CPU has MIPS Binary Translation */
 #define CPU_FEATURE_TLB			13	/* CPU has TLB */
-#define CPU_FEATURE_CSR			14	/* CPU has CSR */
+#define CPU_FEATURE_IOCSR		14	/* CPU has IOCSR */
 #define CPU_FEATURE_WATCH		15	/* CPU has watchpoint registers */
 #define CPU_FEATURE_VINT		16	/* CPU has vectored interrupts */
 #define CPU_FEATURE_CSRIPI		17	/* CPU has CSR-IPI */
diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
index 4446616d497c..6a82ceb6e321 100644
--- a/arch/loongarch/kernel/cpu-probe.c
+++ b/arch/loongarch/kernel/cpu-probe.c
@@ -91,12 +91,23 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
 	unsigned int config;
 	unsigned long asid_mask;
 
-	c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_IOCSR |
-		     LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH;
+	c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_VINT |
+		     LOONGARCH_CPU_WATCH;
 
 	elf_hwcap = HWCAP_LOONGARCH_CPUCFG;
 
 	config = read_cpucfg(LOONGARCH_CPUCFG1);
+
+	if (config & CPUCFG1_ISGR64)
+		set_isa(c, LOONGARCH_CPU_ISA_LA64);
+	else if (config & CPUCFG1_ISGR32)
+		set_isa(c, LOONGARCH_CPU_ISA_LA32S);
+	else
+		set_isa(c, LOONGARCH_CPU_ISA_LA32R);
+	if (config & CPUCFG1_PAGING)
+		c->options |= LOONGARCH_CPU_TLB;
+	if (config & CPUCFG1_IOCSR)
+		c->options |= LOONGARCH_CPU_IOCSR;
 	if (config & CPUCFG1_UAL) {
 		c->options |= LOONGARCH_CPU_UAL;
 		elf_hwcap |= HWCAP_LOONGARCH_UAL;
@@ -222,6 +233,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int
 {
 	uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]);
 	uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]);
+	const char *core_name = "Unknown";
 
 	if (!__cpu_full_name[cpu])
 		__cpu_full_name[cpu] = cpu_full_name;
@@ -232,40 +244,43 @@ static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int
 	switch (c->processor_id & PRID_SERIES_MASK) {
 	case PRID_SERIES_LA132:
 		c->cputype = CPU_LOONGSON32;
-		set_isa(c, LOONGARCH_CPU_ISA_LA32S);
 		__cpu_family[cpu] = "Loongson-32bit";
-		pr_info("32-bit Loongson Processor probed (LA132 Core)\n");
+		core_name = "LA132";
 		break;
 	case PRID_SERIES_LA264:
 		c->cputype = CPU_LOONGSON64;
-		set_isa(c, LOONGARCH_CPU_ISA_LA64);
 		__cpu_family[cpu] = "Loongson-64bit";
-		pr_info("64-bit Loongson Processor probed (LA264 Core)\n");
+		core_name = "LA264";
 		break;
 	case PRID_SERIES_LA364:
 		c->cputype = CPU_LOONGSON64;
-		set_isa(c, LOONGARCH_CPU_ISA_LA64);
 		__cpu_family[cpu] = "Loongson-64bit";
-		pr_info("64-bit Loongson Processor probed (LA364 Core)\n");
+		core_name = "LA364";
 		break;
 	case PRID_SERIES_LA464:
 		c->cputype = CPU_LOONGSON64;
-		set_isa(c, LOONGARCH_CPU_ISA_LA64);
 		__cpu_family[cpu] = "Loongson-64bit";
-		pr_info("64-bit Loongson Processor probed (LA464 Core)\n");
+		core_name = "LA464";
 		break;
 	case PRID_SERIES_LA664:
 		c->cputype = CPU_LOONGSON64;
-		set_isa(c, LOONGARCH_CPU_ISA_LA64);
 		__cpu_family[cpu] = "Loongson-64bit";
-		pr_info("64-bit Loongson Processor probed (LA664 Core)\n");
+		core_name = "LA664";
 		break;
 	default: /* Default to 64 bit */
-		c->cputype = CPU_LOONGSON64;
-		set_isa(c, LOONGARCH_CPU_ISA_LA64);
-		__cpu_family[cpu] = "Loongson-64bit";
-		pr_info("64-bit Loongson Processor probed (Unknown Core)\n");
+		if (c->isa_level & LOONGARCH_CPU_ISA_LA64) {
+			c->cputype = CPU_LOONGSON64;
+			__cpu_family[cpu] = "Loongson-64bit";
+		} else if (c->isa_level & LOONGARCH_CPU_ISA_LA32S) {
+			c->cputype = CPU_LOONGSON32;
+			__cpu_family[cpu] = "Loongson-32bit";
+		} else if (c->isa_level & LOONGARCH_CPU_ISA_LA32R) {
+			c->cputype = CPU_LOONGSON32;
+			__cpu_family[cpu] = "Loongson-32bit Reduced";
+		}
 	}
+
+	pr_info("%s Processor probed (%s Core)\n", __cpu_family[cpu], core_name);
 }
 
 #ifdef CONFIG_64BIT

-- 
2.46.0


  parent reply	other threads:[~2024-09-07 10:17 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-07 10:17 [PATCH 0/5] LoongArch, MIPS: Unify Loongson IOCSR handling Jiaxun Yang
2024-09-07 10:17 ` [PATCH 1/5] LoongArch: Rename cpu_has_csr as cpu_has_iocsr Jiaxun Yang
2024-09-08  2:38   ` Huacai Chen
2024-09-07 10:17 ` Jiaxun Yang [this message]
2024-09-08  2:40   ` [PATCH 2/5] LoongArch: Probe more CPU features from CPUCFG Huacai Chen
2024-09-07 10:17 ` [PATCH 3/5] LoongArch: cpu-probe: Move IOCSR probing out of cpu_probe_common Jiaxun Yang
2024-09-08  2:47   ` Huacai Chen
2024-09-08 10:00     ` Jiaxun Yang
2024-09-07 10:17 ` [PATCH 4/5] LoongArch: Extract IOCSR definitions to standalone header Jiaxun Yang
2024-09-08 16:56   ` kernel test robot
2024-09-07 10:17 ` [PATCH 5/5] MIPS: Loongson64: Use shared IOCSR header Jiaxun Yang
2024-09-07 10:25 ` [PATCH 0/5] LoongArch, MIPS: Unify Loongson IOCSR handling Huacai Chen
2024-09-07 10:30   ` Jiaxun Yang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240907-iocsr-v1-2-0c99b3334444@flygoat.com \
    --to=jiaxun.yang@flygoat.com \
    --cc=chenhuacai@kernel.org \
    --cc=kernel@xen0n.name \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mips@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=loongarch@lists.linux.dev \
    --cc=rafael@kernel.org \
    --cc=tglx@linutronix.de \
    --cc=tsbogend@alpha.franken.de \
    --cc=viresh.kumar@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®